USB interface controller chip
First Claim
Patent Images
1. A USB interface controller formed on an integrated circuit chip comprising:
- a pair of signal ports extending therefrom for being connected with a pair of USB signals from external to the controller chip;
a power node defined on the chip for being connected with a supply voltage; and
a built-in pull-up resistor integrated on the controller chip to be connected between the power node and one of the pair of signal ports, the pull-up resistor having a resistance with a tolerance larger than 5%.
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Abstract
A USB interface controller chip comprises a pair of signal ports for being connecting with a pair of USB signals and a power node for being connecting with a supply voltage characterized in that the controller chip is built-in with a pull-up resistor connected between the power node and one of the pair of signal ports, and the pull-up resistor has a resistance consistent to USB standard but has a tolerance larger than that defined by USB specification.
9 Citations
9 Claims
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1. A USB interface controller formed on an integrated circuit chip comprising:
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a pair of signal ports extending therefrom for being connected with a pair of USB signals from external to the controller chip;
a power node defined on the chip for being connected with a supply voltage; and
a built-in pull-up resistor integrated on the controller chip to be connected between the power node and one of the pair of signal ports, the pull-up resistor having a resistance with a tolerance larger than 5%. - View Dependent Claims (2, 3, 4, 5)
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6. A USB interface device comprising:
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a USB controller defined by an integrated circuit chip, the chip having formed thereon at least first and second signal ports for respective interconnection with external USB signal lines;
the chip including a power node for interconnection with a supply voltage; and
,the chip having integrated therein an internal pull-up resistor extending between the power node and at least the first signal port, the pull-up resistor having a resistance with a tolerance larger than 5%. - View Dependent Claims (7, 8, 9)
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Specification