Method of fabricating thin film transistor array substrate and stacked thin film structure
First Claim
1. A method of fabricating a thin film transistor array substrate, comprising the steps of:
- providing a substrate;
forming a first patterned metallic layer, a dielectric layer, an amorphous silicon layer, a second patterned metallic layer and a passivation layer over the substrate in sequence, wherein the first patterned metallic layer comprises a plurality of scan lines and a plurality of gates connected to the respective scan lines and the second patterned metallic layer comprises a plurality of data lines and a plurality of source/drains connected to the respective data lines;
forming a patterned photoresist layer over the passivation layer, wherein the patterned photoresist layer at least covers the source/drains and its peripheral regions, part of the edges of the patterned photoresist layer has a plurality of thin-out regions with a smaller layer thickness, and each first thin-out region stretches over part of the edge of one source/drain;
removing the passivation layer, the amorphous silicon layer and the dielectric layer exposed by the patterned photoresist layer using the patterned photoresist layer as an etching mask to form a plurality of staircase structure that correspond to the first thin-out regions; and
forming a plurality of pixel electrodes over the substrate such that each pixel electrode at least covers one of the staircase structures and electrically connects with one of the source/drains.
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Abstract
A method of fabricating a thin film transistor array substrate is provided. First, a first patterned metallic layer, a dielectric layer, an amorphous silicon layer, a second patterned metallic layer and a passivation layer are sequentially formed over a substrate. A patterned photoresist layer is formed over the passivation layer. The patterned photoresist layer at least covers the source/drain (formed out of the first patterned metallic layer) as well as the area beside them. The edges of the patterned photoresist layer have a plurality of thin-out regions. Each thin-out region stretches across part of the edge of one source/drain. Thereafter, using the patterned photoresist layer as an etching mask, an etching operation is carried out until the source/drain and its peripheral amorphous silicon layer under the thin-out regions are exposed to form a plurality of staircase structures. Finally, a plurality of pixel electrodes is formed over the substrate to cover the respective staircase structures and electrically connect to one source/drain electrode.
9 Citations
21 Claims
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1. A method of fabricating a thin film transistor array substrate, comprising the steps of:
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providing a substrate;
forming a first patterned metallic layer, a dielectric layer, an amorphous silicon layer, a second patterned metallic layer and a passivation layer over the substrate in sequence, wherein the first patterned metallic layer comprises a plurality of scan lines and a plurality of gates connected to the respective scan lines and the second patterned metallic layer comprises a plurality of data lines and a plurality of source/drains connected to the respective data lines;
forming a patterned photoresist layer over the passivation layer, wherein the patterned photoresist layer at least covers the source/drains and its peripheral regions, part of the edges of the patterned photoresist layer has a plurality of thin-out regions with a smaller layer thickness, and each first thin-out region stretches over part of the edge of one source/drain;
removing the passivation layer, the amorphous silicon layer and the dielectric layer exposed by the patterned photoresist layer using the patterned photoresist layer as an etching mask to form a plurality of staircase structure that correspond to the first thin-out regions; and
forming a plurality of pixel electrodes over the substrate such that each pixel electrode at least covers one of the staircase structures and electrically connects with one of the source/drains. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of fabricating a stacked film structure, comprising the steps of:
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providing a substrate;
forming a dielectric layer, an amorphous silicon layer, a first patterned metallic layer and a passivation layer over a front surface of the substrate in sequence;
forming a patterned photoresist layer over the passivation layer, wherein part of the edges of the patterned photoresist layer has thin-out regions with a smaller layer thickness and each thin-out region stretches over part of the edges of the first patterned metallic layer; and
removing the passivation layer, the amorphous silicon layer and the dielectric layer exposed by the patterned photoresist layer using the patterned photoresist layer as an etching mask and removing the passivation layer under the thin-out regions to form staircase structures that correspond to the thin-out regions. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification