Semiconductor device and method of manufacturing the same

• US 6,916,695 B2
• Filed: 07/03/2002
• Issued: 07/12/2005
• Est. Priority Date: 01/21/2000
• Status: Expired due to Term

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: NEC Corporation
• Inventors: Wakabayashi, Hitoshi, Saito, Yukishige
• Primary Examiner(s): Guerrero, Maria F.
• Application Number:
  US10/188,642
• Publication Number:
  US 20020179975A1
• Time in Patent Office: 1,105 Days
• Field of Search: 438/199, 438/585, 438/587, 438/588, 438/592, 438/593, 438/648, 438/595, 438/597, 438/652, 438/656, 438/685
• US Class Current: 438/199
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 257/915 with titanium nitride portion or region

Abstract

One object of the present invention is to suppress a threshold voltage of at least an n-channel MISFET using a nitride of a high melting point metal at it'"'"'s gate electrode. In order to achieve the object, a gate electrode 109 of a p-channel MISFET is constituted of a titanium nitride film 106 and a tungsten film 107 formed on the film 106 and a gate electrode 110a of an n-channel MISFET is constituted of a titanium nitride film 106a and a tungsten film 107 formed on the film 106a. The titanium nitride film 106a is formed by nitrogen ion implantation in the titanium nitride film 106 to decrease the work function.

Claims

1. A method of manufacturing a semiconductor device having a complementary insulated gate field effect transistor:

said complementary insulated gate field effect transistor comprising a first insulated gate field effect transistor of one conductivity-type having a first gate electrode and a second insulated gate field effect transistor of an opposite conductivity-type having a second gate electrode;

each of said first and second electrodes including a nitride layer of a high melting point metal as at least at a part of said gate electrode;

said method comprising the steps of;

forming said nitride layer of said high melting point metal at said first gate electrode and said second electrode simultaneously; and

introducing thereafter nitrogen into said nitride layer of said high melting point metal only in said first gate electrode between said first and second gate electrodes to enhance the nitrogen density in said nitride layer only in said first gate electrode.

2. A method of manufacturing a semiconductor device having a complementary insulated gate field effect transistor as set force in claim 1, wherein said high melting point metal comprises an element selected from the group consisting of titanium, tungsten and tantalum.

3. A method of manufacturing a semiconductor device having a complementary insulated gate field effect transistor;

said complementary insulated gate field effect transistor comprising a first insulated gate field effect transistor of one conductivity-type having a first gate electrode and a second insulated gate field effect transistor of an opposite conductivity-type having a second gate electrode;

said method comprising steps of;

forming a first nitride layer of a high melting point metal having a first nitrogen density as at least a part of said first gate electrode; and

,

forming a second nitride layer of said high melting point metal having a second nitrogen density different from said first nitrogen density as at least a part of said second gate electrode.

4. A method of manufacturing a semiconductor device having a complementary insulated gate field effect, transistor as set force in claim 3, wherein said high melting point metal comprises an element selected from the group consisting of titanium, tungsten and tantalum.