MOS-gated device having a buried gate and process for forming same

• US 6,916,712 B2
• Filed: 11/09/2001
• Issued: 07/12/2005
• Est. Priority Date: 03/01/1999
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Zeng, Jun, Kocon, Christopher B.
• Primary Examiner(s): Brock, II, Paul E
• Application Number:
  US10/039,319
• Publication Number:
  US 20020056871A1
• Time in Patent Office: 1,341 Days
• Field of Search: 438/270, 438/271, 438/272
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer. A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substantially coplanar with the upper surface of the upper layer of the device.

Claims

1. A process for forming an improved trench MOS-gated device, said process comprising:

(a) forming a doped upper layer on a semiconductor substrate, said upper layer having an upper surface and an underlying drain region;

(b) forming a well region having a first polarity in said upper layer, said well region overlying said drain region;

(c) forming a gate trench mask on said upper surface of said upper layer;

(d) forming a plurality of gate trenches extending from the upper surface of said upper layer through said well region to said drain region, said gate trenches having sidewalls and floors;

(e) covering said sidewalls and floors with a layer of dielectric material;

(f) forming gate electrodes in the trenches to a selected level substantially below the upper surface of said upper level with a conductive gate material,

(g) removing said trench mask from the upper surface of said upper layer;

(h) forming an isolation layer of dielectric material on the upper surface of said upper layer and over said dielectric material covering said sidewalls within said gate trench, said isolation layer overlying said gate material and substantially filling said trench;

(i) removing said isolation layer from the upper surface of said upper layer, a portion of said isolation layer remaining within and substantially filling said trench, and having an upper surface that is proximate to and slightly below the upper surface of said upper layer to increase source contact areas and reduce on resistance,

(j) implanting the entire upper surface of the substrate and diffusing into the surface of the substrate source dopants having a second polarity to form a plurality of heavily doped source regions that extend into the substrate along the sides of the trenches;

(k) implanting and diffusing into the surface a plurality of heavily doped body regions having a first polarity, said body regions overlying the drain region in said upper layer; and

(l) forming a metal contact to said body and source regions over the upper surface of said upper layer.

2. The process of claim 1 wherein the depth of the level of the diffused implants for the source regions is substantially coplanar with the level of the conductive gate material in the trenches.

3. A process for forming an improved trench MOS-gated device, said process comprising:

(a) forming a doped upper layer on a semiconductor substrate, said upper layer having an upper surface and an underlying drain region;

(b) forming a well region having a first polarity in said upper layer, said well region overlying said drain region;

(c) forming a gate trench mask on said upper surface of said upper layer;

(d) forming a plurality of gate trenches extending from the upper surface of said upper layer through said well region to said drain region, said gate trenches having sidewalls and floors;

(e) covering said sidewalls and floors with a layer of dielectric material;

(f) forming gate electrodes in the trenches to a selected level substantially below the upper surface of said upper level with a conductive gate material,

(g) removing said trench mask from the upper surface of said upper layer without removing the layer of dielectric material covering said sidewalls of said trenches;

(h) forming an isolation layer of dielectric material on the upper surface of said upper layer and over said dielectric material covering said sidewalls within said gate trench, said isolation layer overlying said gate material and substantially filling said trench;

(i) removing said isolation layer from the upper surface of said upper layer, a portion of said isolation layer remaining within and substantially filling said trench, and having an upper surface that is proximate to and slightly below the upper surface of said upper layer to increase source contact areas and reduce on resistance;

(j) forming a plurality of heavily doped source regions having a second polarity in said well region, said source regions extending to a selected depth from the upper surface of said upper layer where said selected depth is substantially coplanar with the level of the conductive gate material in the trench, said step of forming the plurality of heavily doped source regions comprising implanting the entire upper surface of said substrate with ions of said second polarity, then forming a body mask on the upper surface of said substrate;

(k) forming a plurality of heavily doped body regions having a first polarity at the upper surface of said upper layer, said body regions overlying the drain region in said upper layer, said step of forming a plurality of heavily doped body regions comprising doping the upper surface of said substrate with a dopant of said first polarity, then removing said body mask; and

(l) forming a metal contact to said body and source regions over the upper surface of said upper layer.

4. The process of claim 3 wherein said substrate comprises monocrystalline silicon.

5. The process of claim 3 wherein said upper layer comprises an epitaxial layer.

6. The process of claim 3 wherein one of said source regions surround said body regions and the source regions are separated from each other by trenches.

7. The process of claim 3 wherein said dielectric material covering said sidewalls and said floor, and forming said isolation layer in said gate trench comprises silicon dioxide.

8. The process of claim 3 wherein said conductive gate material within said gate trench is selected from the group consisting of a metal, a silicide, and doped polysilicon.

9. The process of claim 3 wherein said first polarization polarity is P and said second polarity is N.

10. The process of claim 3 wherein said device is selected from the group consisting of a power MOSFET, an insulated gate bipolar transistor, an MOS-controlled thyristor, and an accumulation FET.

11. A process for forming an improved trench MOS-gated device, said process comprising:

(a) forming a doped upper layer on a semiconductor substrate, said upper layer having an upper surface and an underlying drain region;

(b) forming a well region having a first polarity in said upper layer, said well region overlying said drain region;

(c) forming a gate trench mask on said upper surface of said upper layer;

(d) forming a gate trench extending from the upper surface of said upper layer through said well region to said drain region, said gate trench having sidewalls and a floor;

(e) covering said sidewalls and floor with a layer of gate dielectric material;

(f) forming gate electrodes in the trenches to a selected level with a conductive gate material, said selected level being substantially below the upper surface of said upper level, a portion of said gate dielectric material covering said sidewalls from said selected level to proximate said upper surface of said upper layer;

(g) removing said trench mask from the upper surface of said upper layer without removing said portion of said gate dielectric material covering said sidewalls from said selected level to proximate said upper surface of said upper layer;

(h) forming an isolation layer of dielectric material on the upper surface of said upper layer and over said dielectric material covering said sidewalls within said gate trench, said isolation layer overlying said gate material and substantially filling said trench;

(i) removing said isolation layer from the upper surface of said upper layer, a portion of said isolation layer remaining within and substantially filling said trench, and having an upper surface that is proximate to and slightly below the upper surface of said upper layer to increase source contact areas and reduce on resistance,

(j) forming a plurality of heavily doped source regions having a second polarity in said well region, said source regions extending to a selected depth from the upper surface of said upper layer where said selected depth is substantially coplanar with the level of the conductive gate material in the trench, said step of forming a plurality of heavily doped source regions comprising implanting the entire upper surface of said substrate with ions of said second polarity, then forming a body mask on the upper surface of said substrate;

(k) forming a plurality of heavily doped body regions having a first polarity at the upper surface of said upper layer, said body regions overlying the drain region in said upper layer, said step of forming a plurality of heavily doped body regions comprising doping the upper surface of said substrate with a dopant of said first polarity, then removing said body mask; and

(l) forming a metal contact to said body and source regions over the upper surface of said upper layer.