Method and apparatus for non-conductively interconnecting integrated circuits

• US 6,916,719 B1
• Filed: 12/10/1999
• Issued: 07/12/2005
• Est. Priority Date: 06/24/1993
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: David B. Salzman, Thomas F. Knight
• Inventors: Salzman, David B., Knight, Thomas F.
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Duong, Khanh B.
• Application Number:
  US09/459,108
• Time in Patent Office: 2,041 Days
• Field of Search: 438/107, 438/109, 438/128, 438/129, 438/238, 438/239, 438/171, 438/190, 438/210, 438/329, 438/381, 438/901, 438/6, 438/10, 361/760, 361/738, 361/763, 361/766, 361/830, 257/664
• US Class Current: 438/381
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/312 by capacitive methods
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01043 : Technetium [Tc]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01092 : Uranium [U]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10S 257/924 : with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap

Abstract

Methods and apparatus are described for capacitively signaling between different semiconductor chips and modules without the use of connectors, solder bumps, wire-bond interconnections or the like. Preferably, pairs of half-capacitor plates, one half located on each chip, module or substrate are used to capacitively couple signals from one chip, module or substrate to another. The use of plates relaxes the need for high precision alignment as well as reduces the area needed to effect signaling, and reduces or eliminates the requirements for exotic metallurgy.

Claims

1. A method of coupling signals between electronic devices in a modular electronic system, said method comprising the steps of:

locating a first subset of said electronic devices and a plurality of half-capacitors on a first semiconductor chip;

locating a second subset of said electronic devices and a plurality of half-capacitors on a second semiconductor chip; and

,

aligning and affixing said first and second chips so as to capacitively couple said first and second chips using at least some of the half-capacitors on each of said chips.

2. A method of coupling signals between electronic devices in a modular electronic system as defined in claim 1 wherein the first and second chips are affixed to a base substrate thereby capacitively coupling said first and second chips via said substrate.

3. A method of capacitively coupling signals between first and second chips, each said chip having a plurality of half-capacitors, said method comprising the steps of:

affixing said first chip to a substrate;

aligning said second chip to said first chip; and

,

affixing said second chip to said substrate, thereby capacitively coupling corresponding half-capacitors on said first and second chips and providing direct capacitive coupling between said first and second chips.

4. A method of fabricating an integrated circuit module, comprising:

providing a plurality of first dice, said first dice each having half-capacitors formed on a surface thereof;

providing a plurality of second dice, said second dice each having half-capacitors formed on a surface thereof; and

arranging said first dice so that each of said first dice overlaps at least three of said second dice, and each of said second dice overlaps at least three of said first dice, thereby defining overlap areas,

wherein at least some half-capacitors of said plurality of first dice are configured to be capacitively coupled to corresponding half-capacitors of said second dice in said overlap areas.

5. The method of claim 4 wherein providing said plurality of first dice and second dice include forming a dielectric layer on some of said first dice and second dice, so that half-capacitors in said overlap areas are spaced apart.

6. The method of claim 4 wherein said plurality of first dice are rectangles.

7. The method of claim 4 wherein said plurality of second dice are rectangles.

8. The method of claim 6 wherein said plurality of second dice are squares.

9. The method of claim 4 wherein said plurality of first and second dice are shaped as octagons.

10. The method of claim 4 further comprising:

arranging said first dice to form a first two-dimensional repeating pattern; and

arranging said second dice to form a second two-dimensional repeating pattern.

11. The method of claim 4 further comprising:

capacitively coupling some half-capacitors of said first dice to some half-capacitors of said second dice in said overlap areas.

12. A method of fabricating an integrated circuit module, comprising:

providing a plurality of first dice, said first dice each having first half-capacitors formed on a surface thereof;

providing a plurality of second dice, said second dice each having second half-capacitors formed on a surface thereof; and

arranging said first dice so that each first die overlaps at least two of said second dice, thereby defining overlap areas, wherein said first half-capacitors located in said overlap areas are configured to be capacitively coupled to some of said second half-capacitors,

wherein said first dice or said second dice have raised areas relative to said surfaces, the raised areas of each of said first or said second die contacting an area on one of the overlapping die.

13. The method of claim 12 wherein each of said first dice and said second dice have raised areas relative to said surfaces, and the signals pads in said overlapping areas are disposed in between said raised areas.

14. The method of claim 12 wherein each of said raised areas of said first dice contact one of the raised areas of said second dice.

15. The method of claim 12 wherein said plurality of first dice are on a plane that is above each of said plurality of second dice.

16. The method of claim 12 wherein the plurality of first dice comprises half-capacitors that do not overlap one of the plurality of second dice.

17. The method of claim 12 wherein arranging said first dice further comprises arranging said first dice so that each first die overlaps at least three of said second dice.

18. A method of fabricating an integrated circuit module, comprising:

providing a plurality of first dice, said first dice each having half-capacitors formed on a surface thereof;

providing a plurality of second dice, said second dice each having half-capacitors formed on a surface thereof;

arranging said first dice so that each first die overlaps at least four of said second dice, thereby defining overlap areas; and

aligning said first dice so that half-capacitors thereof located in said overlap areas are configured to be capacitively coupled to some half-capacitors of said second dice.

19. The method of claim 18 wherein said plurality of first dice are on a plane that is above each of said plurality of second dice.

20. The method of claim 18 wherein each of the plurality of first dice comprises four sides, and each of said first dice overlaps one of said plurality of second dice on each of said four sides of said first dice.

21. The method of claim 18 wherein the plurality of first dice comprises half-capacitors that do not overlap one of the plurality of second dice.

22. The method of claim 18 wherein at least some of said half-capacitors in said plurality of first dice are capacitively coupled to a chip substrate within said first dice.

23. The method of claim 18 wherein at least some of said half-capacitors in said plurality of first dice are coupled to a chip substrate through vias within said first dice.