One transistor SOI non-volatile random access memory cell

• US 6,917,078 B2
• Filed: 08/30/2002
• Issued: 07/12/2005
• Est. Priority Date: 08/30/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US10/232,846
• Publication Number:
  US 20040041208A1
• Time in Patent Office: 1,047 Days
• Field of Search: 257347-354, 257/324
• US Class Current: 257/347
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein.

Claims

1. A silicon-on-insulator field effect transistor (SOI-FET), comprising:

a body region formed over a substrate with a buried insulator layer disposed between the body region and the substrate, wherein the body region includes a charge trapping region;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

2. The SOI-FET of claim 1, wherein the SOI-FET has a first threshold voltage associated with a non-volatile first memory state when excess charges are trapped in the charge trapping region, and a second threshold voltage associated with a second memory state when trapped charges in the charge trapping region are neutralized.

3. The SOI-FET of claim 1, wherein the charge trapping region is located in the body region proximate to an interface between the body region and the buried insulator layer.

4. The SOI-FET of claim 1, wherein the charge trapping region includes a charge trapping layer located in the body region at a depth of at least 200 Å

from a top surface of the body region.

5. The SOI-FET of claim 1, wherein the charge trapping region includes a silicon-rich-insulator (SRI) layer located in the body region proximate to an interface between the body region and the buried insulator layer.

6. The SOI-FET of claim 1, wherein the charge trapping region includes a silicon-rich-nitride (SRN) layer located in the body region proximate to an interface between the body region and the buried insulator layer.

7. The SOI-FET of claim 1, wherein a potential difference is applied between the gate and the substrate to direct excess charges towards the charge trapping region.

8. The SOI-FET of claim 1, wherein the charge trapping region is capable of storing charges for a length of time to provide the SOI-FET with non-volatility.

9. The SOI-FET of claim 1, wherein the charge trapping region is capable of storing charges for a length of time to provide the SOI-FET with data integrity for up to ten years without refresh.

10. The SOI-FET of claim 1, wherein the charge trapping region is capable of trapping charges and is capable of de-trapping/neutralizing charges such that the SOI-FET has fast read and write operations on the order of nanoseconds.

11. The SOI-FET of claim 1, wherein the charge trapping region is capable of trapping charges and is capable of de-trapping/neutralizing charges such that the SOI-FET is capable of performing read and write operations using voltage pulses no greater in magnitude than a power supply voltage.

12. The SOI-FET of claim 1, wherein the SOI-FET has a cell size of 4F².

13. The SOI-FET of claim 1, wherein a channel conductance of the SOI-FET is used to determine whether the SOI-FET is in the first memory state or the second memory state.

14. The SOI-FET of claim 13, wherein the channel conductance is determined using a source current of the SOI-FET.

15. A silicon-on-insulator field effect transistor (SOI-FET), comprising:

a body region formed over a substrate with a buried insulator layer disposed between the body region and the substrate, wherein the body region includes a charge trapping region;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer,

wherein;

the charge trapping region is capable of storing charges for a length of time to provide the SOI-FET with non-volatile data integrity for up to ten years without refresh;

the charge trapping region is capable of trapping charges and is capable of de-trapping/neutralizing charges such that the SOI-FET has fast read and write operations on the order of nanoseconds, and such that the SOI-FET is capable of performing read and write operations using voltage pulses no greater in magnitude than a power supply voltage; and

the SOI-FET has a cell size of 4F².

16. A silicon-on-insulator field effect transistor (SOI-FET), comprising:

a body region formed over a substrate with a buried insulator layer disposed between the body region and the substrate, wherein the body region includes a silicon-rich-insulator (SRI) layer;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer,

wherein the SOI-FET has a first threshold voltage associated with a non-volatile first memory state when excess charges are trapped in the SRI layer, and a second threshold voltage associated with a second memory state when trapped charges in the SRI layer are neutralized.

17. The SOI-FET of claim 16, wherein the SRI layer includes a silicon-rich-nitride (SRN) layer.

18. The SOI-FET of claim 16, wherein the SRI layer includes a silicon-rich-oxide (SRO) layer.

19. The SOI-FET of claim 16, wherein:

the body region is doped with p-type impurities;

both the first diffusion region and the second diffusion region are doped with n+ diffusion regions; and

a number of excess holes generated in the body region are trapped in the SRI layer.

20. The SOI-FET of claim 16, wherein:

the body region is doped with n-type impurities;

both the first diffusion region and the second diffusion region are doped with p+ diffusion regions; and

a number of excess electrons generated in the body region are trapped in the SRI layer.

21. The SOI-FET of claim 16, wherein a potential difference is applied between the gate and the substrate to provide a charge drift toward the SRI layer.

22. The SOI-FET of claim 16, wherein the charge to be trapped in the SRI layer is generated by impact ionization in a field effect transistor (FET) mode of operation.

23. The SOI-FET of claim 16, wherein the charge to be trapped in the SRI layer is generated in a lateral parasitic bipolar junction transistor (BJT) mode of operation.

24. A memory cell, comprising:

a substrate;

a buried insulator layer formed on the substrate; and

a transistor formed on the buried insulator layer, including;

a floating body region, including a charge trapping region within the floating body region;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

25. The memory cell of claim 24, wherein the charge trapping region is located in the body region proximate to an interface between the body region and the buried insulator layer.

26. The memory cell of claim 24, wherein the charge trapping region is at a depth of at least 200 Å

from a top surface of the body region.

27. The memory cell of claim 24, wherein the charge trapping region includes a silicon-rich-insulator (SRI) layer located in the body region proximate to an interface between the body region and the buried insulator layer.

28. The memory cell of claim 24, wherein the charge trapping region includes a silicon-rich-nitride (SRN) layer located in the body region proximate to an interface between the body region and the buried insulator layer.

29. The memory cell of claim 24, further comprising a substrate contact to apply a substrate voltage and produce an electromotive force (EMF) field across the floating body region to direct excess charges to the charge trapping region.

30. A memory cell, comprising:

a substrate;

a buried oxide (BOX) insulator layer formed on the substrate; and

a silicon-on-insulator field effect transistor (SOI-FET) formed on the BOX insulator layer, including;

a floating body region, including a silicon-rich-insulator (SRI) layer within the floating body region;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer.

31. The memory cell of claim 30, wherein the SRI layer is located in the body region proximate to an interface between the body region and the BOX insulator layer.

32. The memory cell of claim 30, wherein the SRI layer includes a silicon-rich-nitride (SRN) layer.

33. The memory cell of claim 30, wherein the SRI layer includes a silicon-rich-oxide (SRO) layer.

34. A memory cell, comprising:

a substrate having a substrate contact to apply a substrate voltage;

a buried oxide (BOX) insulator layer formed on the substrate; and

a silicon-on-insulator field effect transistor (SOI-FET) formed on the BOX insulator layer, including;

a floating body region, including a silicon-rich-insulator (SRI) layer within the floating body region;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region, the first diffusion region having a drain contact to apply a drain voltage, and the second diffusion region having a source contact;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer, the gate having a gate contact to apply a gate voltage.

35. The memory cell of claim 34, wherein operation of the SOI-FET generates a charge in the floating body region, and an electro-motive force (EMF) field is applied between the substrate and the gate to direct the charge to the SRI layer.

36. The memory cell of claim 34, wherein the charge is generated in the floating body region due to impact ionization when the SOI-FET is operated in a field effect transistor (FET) mode of operation.

37. The memory cell of claim 34, wherein the charge is generated in the floating body region when the SOI-FET is operated in a lateral parasitic bipolar junction transistor (BJT) mode of operation.

38. The memory cell of claim 34, wherein:

a first non-volatile memory state is associated with a first threshold voltage;

a second memory state is associated with a second threshold voltage;

the SRI layer is adapted to hold trapped charges in the body region to provide the first threshold voltage; and

the trapped charges are neutralized to provide the second threshold voltage.

39. The memory cell of claim 38, wherein a current through the source contact is used to determine whether the memory cell is in one of the first memory state and the second memory state.

40. A memory cell, comprising:

a substrate;

a buried insulator layer formed on the substrate; and

a transistor formed on the insulator layer, including;

means to trap excess charges in a floating body of the transistor;

means to generate excess charges to be trapped in the floating body to provide a first memory state; and

means to neutralize trapped charges in the floating body to provide a second memory state.

41. The memory cell of claim 40, wherein means to trap excess charges in a floating body of the transistor includes a charge trapping layer formed in the floating body of the transistor.

42. The memory cell of claim 40, wherein means to generate excess charges to be trapped in the floating body includes operating the transistor in a saturated mode such that charges are generated through impact ionization.

43. The memory cell of claim 40, wherein means to generate charges to be trapped in the floating body includes creating charges in the floating body using a lateral parasitic bipolar junction transistor.

44. The memory cell of claim 40, wherein means to neutralize trapped charges in the floating body includes means to forward bias a diode between the floating body and a diffusion region of the transistor.

45. The memory cell of claim 40, wherein means to trap excess charges in a floating body of the transistor includes a silicon-rich-insulator (SRI) layer formed in the floating body of the transistor.

46. The memory cell of claim 45, wherein the SRI layer includes a silicon-rich-nitride (SRN) layer.

47. A memory device, comprising:

a memory array, including;

a substrate;

a buried insulator layer formed on the substrate; and

a number of memory cells formed on the buried insulator layer and organized in a number of rows and a number of columns, each of the number of memory cells including a transistor formed on the buried insulator layer, the transistor including a floating body region that includes a charge trapping region, the transistor further including a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region, a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer; and

control circuitry operably connected to the memory array to write selected memory cells and to read selected memory cells.

48. The memory device of claim 47, wherein the charge trapping region includes a silicon-rich-insulator (SRI) layer located in the floating body region near an interface between the floating body region and the buried insulator layer.

49. The memory device of claim 47, wherein:

the control circuitry includes word line select and power circuitry to provide a desired voltage pulse to a word line for a selected row of memory cells; and

the word line is connected to the gate for each memory cell in the row of memory cells.

50. The memory device of claim 47, wherein:

the control circuitry includes bit line select and power circuitry to provide a desired voltage pulse to a bit line for a selected column of memory cells; and

the bit line is connected to the first diffusion region for each memory cell in the column of memory cells.

51. The memory device of claim 47, wherein, for a selected memory cell, the control circuitry includes circuitry to provide a desired word voltage pulse to the gate of the selected memory cell, a desired bit voltage pulse to the first diffusion region of the selected memory cell, and a desired substrate voltage pulse to the substrate of the selected memory cell.

52. The memory device of claim 47, wherein the control circuitry includes read circuitry to use a source current for a selected memory cell to determine the state of the selected memory cell.

53. The memory device of claim 47, wherein the control circuitry includes substrate control circuitry to provide a desired voltage pulse to the substrate.

54. The memory device of claim 53, wherein:

the memory array includes more than one substrate region; and

the substrate control circuitry is adapted to provide a desired voltage pulse to a selected substrate region.

55. A memory device, comprising:

a memory array, including;

a substrate;

a buried insulator layer formed on the substrate; and

a number of one-transistor memory cells formed on the buried insulator layer and organized in a number of rows and a number of columns, each of the number of memory cells including one transistor formed on the buried insulator layer, the transistor including a floating body region that includes a silicon-rich-insulator (SRI) layer, the transistor further including a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region, a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer; and

control circuitry operably connected to the memory array to write selected memory cells and to read selected memory cells.

56. The memory device of claim 55, wherein the SRI layer is located in the floating body region near an interface between the floating body region and the buried insulator layer.

57. The memory device of claim 55, wherein the control circuitry includes circuitry to write to a selected cell by providing a desired voltage pulse to the gate of the selected memory cell, a desired voltage pulse to the first diffusion region of the selected memory cell, and a desired voltage pulse to the substrate.

58. The memory device of claim 55, wherein the control circuitry includes circuitry to read a selected cell by providing a desired voltage to the gate of the selected memory cell, a desired voltage to the first diffusion region of the selected memory cell, and a desired voltage pulse to the substrate, and by using a source current of the transistor to determine a memory state of the memory cell.

59. An electronic system, comprising:

a processor; and

at least one memory cell to communicate with the processor, the memory cell including a silicon-on-insulator field effect transistor (SOI-FET), including;

a body region formed over a substrate with a buried insulator layer disposed between the body region and the substrate, wherein the body region includes a charge trapping region;

a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region;

a gate insulator layer formed over the channel region; and

a gate formed over the gate insulator layer,

wherein the SOI-FET has a first threshold voltage associated with a first memory state, and a first threshold voltage associated with a non-volatile first memory state when excess charges are trapped in the charge trapping region, and a second threshold voltage associated with a second memory state when trapped charges in the charge trapping region are neutralized.

60. The system of claim 59, wherein the charge trapping region is located in the body region proximate to an interface between the body region and the buried insulator layer.

61. The system of claim 59, wherein the charge trapping region is at a depth of at least 200 Å

from a top surface of the body region.

62. The system of claim 59, wherein the charge trapping region includes a silicon-rich-insulator (SRI) layer located in the body region proximate to an interface between the body region and the buried insulator layer.

63. The system of claim 59, wherein the charge trapping region includes a silicon-rich-nitride (SRN) layer located in the body region proximate to an interface between the body region and the buried insulator layer.

64. A method of forming a non-volatile memory cell, comprising:

providing a substrate;

forming a buried oxide (BOX) insulator on the substrate; and

forming a silicon-on-insulator field effect transistor (SOI-FET) over the BOX insulator, including forming a charge trapping region in a body region of the SOI-FET.

65. The method of claim 64, wherein forming a charge trapping region includes forming a silicon-rich-nitride (SRN) layer.

66. The method of claim 64, wherein forming a charge trapping region includes:

ion implanting silicon and ammonia (NH₃) into the body region using a predetermined energy and concentration to achieve a desired refractive index; and

performing a post-implant inert anneal of the body region.

67. The method of claim 64, wherein forming a charge trapping region includes:

ion implanting an active silicon source with an active nitrogen into the body region using a predetermined energy and concentration to achieve a desired refractive index; and

performing a post-implant inert anneal of the body region.

68. The method of claim 64, further comprising forming a substrate contact to provide a substrate voltage pulse to the substrate, a gate line contact to provide a gate voltage pulse to a gate of the SOI-FET, a bit line contact to provide a bit line voltage pulse to a first diffusion region of the SOI-FET, and a source line contact.