Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice

• US 6,917,219 B2
• Filed: 03/12/2003
• Issued: 07/12/2005
• Est. Priority Date: 03/12/2003
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: New, Bernard J.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Nguyen, Linh V.
• Application Number:
  US10/387,622
• Publication Number:
  US 20040178819A1
• Time in Patent Office: 853 Days
• Field of Search: 326 37- 41
• US Class Current: 326/41
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11616 Chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1412 Layout
• CPC Class Codes: H01L 2224/16148 the bump connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/81898 Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other
• CPC Class Codes: H01L 2224/819 with the bump connector not providing any mechanical bonding
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11803 : using field effect technology
• CPC Class Codes: H01L 27/11898 : Input and output buffer/driver structures
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is disposed on a first die whereas the configuration memory is disposed on a second die. The second die is bonded to the first die in stacked relation. Each bit of configuration data passes from the second die to the first die through a pair of micropads. One micropad of the pair is disposed on the first die and the other micropad of the pair is disposed on the second die. When the first die and second die are brought together in face-to-face relation, the two micropads form an electrical connection through which the configuration data bit passes from the second die to the first die.

Claims

1. A device, comprising:

a configurable logic portion disposed on a first structure; and

a configuration memory disposed on a second structure, the first structure physically separable from the second structure, the first structure and the second structure being disposed in a stacked relation to one another, wherein the first structure is coupled to the second structure such that configuration data is communicated from the configuration memory to the configurable logic portion and configures the configurable logic portion, wherein one of the first and second structures comprises a protruding alignment structure, and the other of the first and second structures comprises a recessed alignment structure, the protruding alignment structure engaging the recessed alignment structure when the first structure and the second structure are in said stacked relation.

2. The device of claim 1, wherein the device is a field programmable gate array, and wherein the configurable logic portion comprises configurable logic blocks, input/output blocks, and a programmable interconnect structure.

3. The device of claim 1, wherein the configurable logic portion comprises a plurality of pass transistors, and wherein the configuration memory comprises a plurality of memory cells, each of the memory cells storing a configuration data bit that controls a corresponding one of the plurality of pass transistors.

4. The device of claim 1, wherein the first structure comprises a first micropad, and wherein the second structure comprises a second micropad, the first structure being coupled to the second structure such that the first micropad is in electrical communication with the second micropad.

5. The device of claim 1, wherein the configurable logic portion is disposed on a face of the first structure, and wherein the configuration memory is disposed on a face of the second structure, and wherein the first structure is bonded to the second structure in a face-to-face relation.

6. The device of claim 1, wherein the first structure and the second structure each have a face and a backside, wherein the configurable logic portion is disposed on the face of the first structure, wherein the configuration memory is disposed on the face of the second structure, and wherein the face of the first structure is bonded to the backside of the second structure.

7. The device of claim 1, wherein the first structure and the second structure each have a face and a backside, wherein the configurable logic portion is disposed on the face of the first structure, wherein the configuration memory is disposed on the face of the second structure, and wherein the face of the second structure is bonded to the backside of the first structure.

8. The device of claim 1, wherein the first structure has a face and a backside surface, and wherein the second structure has a face and a backside surface, the configurable logic portion being disposed on the face of the first structure, and wherein the configuration memory is disposed on the face of the second structure, and wherein the first structure is coupled to the second structure in a face-to-face relation.

9. The device of claim 1, wherein the configuration memory comprises a plurality of configuration memory cells.

10. The device of claim 1, wherein the configuration memory comprises first voltage distribution grid, a second voltage distribution grid, and a plurality of micropads, each of the micropads being connected to a selected one of the first and second voltage distribution grids.

11. The device of claim 1, wherein the configuration memory contains no memory cells that store configuration data bits.

12. The device of claim 1, wherein the configuration memory provides configuration data bits by providing connections from the configurable logic portion to logic one and logic zero voltage sources.

13. A method of forming a device, comprising:

stacking a first structure and a second structure together, the first structure physically separable from the second structure, and electrically connecting the first structure to the second structure such that a configuration data bit maintained on the second structure is communicated to the first structure, the configuration data bit configuring configurable logic on the first structure, wherein one of the first and second structures includes a protruding alignment feature, and the other of the first and second structures includes a recessed alignment feature, the protruding alignment feature engaging the recessed alignment feature when the first structure and the second structure are stacked together.

14. The method of claim 13, wherein the first structure and the second structure together comprise a field programmable gate array, the configurable logic comprising a pass transistor of a programmable interconnect structure of the field programmable gate array.

15. The method of claim 13, wherein the first structure comprises a first micropad, and wherein the second structure comprises a second micropad, and wherein the configuration data bit is communicated from the second structure to the first structure through an electrical connection established between the second micropad and the first micropad.

16. The method of claim 13, wherein the first structure and the second structure together comprise a programmable logic device, the programmable logic device comprising a configuration memory and a configurable logic portion, wherein substantially all of the configuration memory is disposed on the second structure, and wherein substantially all of the configurable logic portion is disposed on the first structure.

17. An integrated circuit, comprising:

a programmable logic portion including a plurality of configurable elements; and

a plurality of micropads disposed across a surface of the integrated circuit, each of the micropads being coupled to a corresponding one of the plurality of configurable elements, wherein at least some of the plurality of micropads are one of protruding micropads and recessed micropads.

18. The integrated circuit of claim 17, wherein each of the micropads is usable to receive a bit of configuration data onto the integrated circuit.

19. A method of forming an integrated circuit device comprising:

providing a first device having configurable circuitry for implementing a logic function and a plurality of first micropads disposed in a pattern on a surface of the first device;

providing a second device having circuitry for providing configuration signals and a plurality of second micropads disposed in the pattern, the second device being adapted to be coupled to the surface of the first device in a stacked relation such that each of the first micropads on the first device couples with a corresponding one of the second micropads on the second device wherein at least some of the plurality of micropads are one of protruding micoropads and recessed micropads.

20. The method of claim 19, further comprising:

providing a third device that includes a plurality of third micropads disposed in the pattern, the third device being adapted to be coupled to the surface of the first device in a stacked relation such that each of the plurality of first micropads on the first device couples with a corresponding one of the third micropads on the third device, wherein the second device and the third device have different circuitry.

21. The method of claim 19, wherein each of the second micropads on the second device is hardwired to receive one of a first logic value and a second logic value.

22. The method of claim 19, wherein the second device is a mask-programmable device, wherein at least some of the second micropads are programmably couplable to one of a first voltage distribution grid on the second device and a second voltage distribution grid on the second device.

23. A method, comprising:

coupling a first device having configurable logic to a second device having structure for providing configuration data bits in a stacked relation such that the configuration data bits stored on the second device are communicated from the second device to the configurable logic on the first device such that the configurable logic on the first device is configured to realize a user-defined circuit; and

providing a third device having the configurable logic of the first device and further structure supplying each of the data bits of the second device such that the third device implements the same user-defined circuit as does the first device.

24. The method of claim 23, further comprising:

using the first device and the second device that are in a stacked relation to test the user-defined circuit prior to said providing the third device.

25. The method of claim 23, the further structure of the third device comprises a power supply grid and a ground potential grid, each of the plurality of micropads of the third device being coupled to one of the power supply grid and the ground potential grid.

26. The method of claim 23, wherein the first device and the second device that are in a stacked relation together comprise a field programmable gate array.

27. The method of claim 23, wherein the third device comprises a factory programmed gate array.

28. The method of claim 23 wherein

the step of providing a third device having the configurable logic of the first device and further structure comprises

forming a logic portion having a structure substantially identical to a structure of the first device except for a top mask layer;

and

adding to the logic portion a substitute top mask layer having micropads corresponding to micropads of the first device and a grid of metal lines for supply high and low voltages to the logic portion.

29. The method of claim 23 wherein:

the step of providing a third device having the configurable logic of the first device and further structure comprises

forming a logic portion having a structure substantially identical to a structure of the first device; and

adding to the logic portion a top mask layer having a grid of metal lines for supply high and low voltages to the logic portion.

30. A device comprising:

a configurable logic portion disposed on a first die; and

a configuration memory disposed on a second die, the first die and the second die being disposed in a stacked relation to one another, wherein the first die is coupled to the second die such that configuration data is communicated from the configuration memory to the configurable logic portion and configures the configurable logic portion;

wherein one of the first and second dice includes a protruding alignment feature, and wherein the other of the first and second dice includes a recessed alignment feature, the protruding alignment feature engaging the recessed alignment feature when the first die and the second die are stacked together.

31. The device of claim 30, wherein the device is a field programmable gate array, and wherein the configurable logic portion comprises configurable logic blocks, input/output blocks, and a programmable interconnect structure.

32. The device of claim 30, wherein the configurable logic portion comprises a plurality of pass transistors, and wherein the configuration memory comprises a plurality of memory cells, each of the memory cells storing a configuration data bit that controls a corresponding one of the plurality of pass transistors.

33. The device of claim 30, wherein the first die comprises a first micropad, and wherein the second die comprises a second micropad, the first die being coupled to the second die such that the first micropad is in electrical communication with the second micropad.

34. The device of claim 30, wherein the configuration memory comprises first voltage distribution grid, a second voltage distribution grid, and a plurality of micropads, each of the micropads being connected to a selected one of the first and second voltage distribution grids.

35. The device of claim 30, wherein the configuration memory provides configuration data bits by providing connections from the configurable logic portion to logic one and logic zero voltage sources.

36. A method of forming a device, comprising:

stacking a first die and a second die together and electrically connecting the first die to the second die such that a configuration data bit maintained on the second die is communicated to the first die, the configuration data bit configuring configurable logic on the first die;

wherein one of the first and second dice includes a protruding alignment feature, and wherein the other of the first and second dice includes a recessed alignment feature, the protruding alignment feature engaging the recessed alignment feature when the first die and second die are stacked together.

37. The method of claim 36, wherein the first die and the second die together comprise a field programmable gate array, the configurable logic comprising a pass transistor of a programmable interconnect structure of the field programmable gate array.

38. The method of claim 36, wherein the first die comprises a first micropad, and wherein the second die comprises a second micropad, and wherein the configuration data bit is communicated from the second die to the first die through an electrical connection established between the second micropad and the first micropad.

39. The method of claim 36, wherein the first die and the second die together comprise a programmable logic device, the programmable logic device comprising a configuration memory and a configurable logic portion, wherein substantially all of the configuration memory is disposed on the second die, and wherein substantially all of the configurable logic portion is disposed on the first die.