Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges and systems including same
First Claim
1. A computer system comprising:
- an input device;
an output device;
a processor device operably coupled to said input device and said output device; and
a memory device operably coupled to said processor device, said memory device including a skewed logic device, said skewed logic device selected from one of a skewed inverter rising logic device, a skewed inverter falling logic device, a skewed buffer rising logic device, a skewed buffer falling logic device, a skewed NOR falling logic device, a skewed NOR rising logic device, a skewed NAND falling logic device and a skewed NAND rising logic device, each of said logic devices including;
a logic gate having a large channel width ratio for receiving an input signal and rapidly propagating an output edge onto an output signal in response to an input edge of the input signal;
a reset network connected in parallel with said logic gate for resetting said output signal after said output edge has been propagated onto said output signal; and
a feedback delay circuit connected in parallel with said reset network for delaying and returning said output signal back to said reset network.
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Abstract
The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.
43 Citations
13 Claims
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1. A computer system comprising:
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an input device;
an output device;
a processor device operably coupled to said input device and said output device; and
a memory device operably coupled to said processor device, said memory device including a skewed logic device, said skewed logic device selected from one of a skewed inverter rising logic device, a skewed inverter falling logic device, a skewed buffer rising logic device, a skewed buffer falling logic device, a skewed NOR falling logic device, a skewed NOR rising logic device, a skewed NAND falling logic device and a skewed NAND rising logic device, each of said logic devices including;
a logic gate having a large channel width ratio for receiving an input signal and rapidly propagating an output edge onto an output signal in response to an input edge of the input signal;
a reset network connected in parallel with said logic gate for resetting said output signal after said output edge has been propagated onto said output signal; and
a feedback delay circuit connected in parallel with said reset network for delaying and returning said output signal back to said reset network. - View Dependent Claims (2, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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3. A semiconductor substrate comprising:
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a plurality of integrated circuit (IC) dice, each IC die of said plurality of IC dice including a skewed logic device, said skewed logic device selected from one of a skewed inverter rising logic device, a skewed inverter falling logic device, a skewed buffer rising logic device, a skewed buffer falling logic device, a skewed NOR falling logic device, a skewed NOR rising logic device, a skewed NAND falling logic device and a skewed NAND rising logic device, each of said logic devices including;
a logic gate having a large channel width ratio for receiving an input signal and rapidly propagating an output edge onto an output signal in response to an input edge of the input signal;
a reset network connected in parallel with said logic sate for resetting said output signal after said output edge has been propagated onto said output signal; and
a feedback delay circuit connected in parallel with said reset network for delaying and returning said output signal back to said reset network. - View Dependent Claims (4)
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Specification