Method and apparatus for use in switched capacitor systems

• US 6,917,321 B1
• Filed: 05/21/2000
• Issued: 07/12/2005
• Est. Priority Date: 05/21/2000
• Status: Expired due to Term

• Current Assignee: Xueshan Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: Analog Devices, Inc.
• Inventors: Ferguson, Paul F. Jr., Haurie, Xavier S.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/575,562
• Time in Patent Office: 1,878 Days
• Field of Search: 341/144, 341/150, 341/118, 341/146
• US Class Current: 341/144
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

Systems and methods receive a digital signal and generate an analog signal indicative thereof. In one embodiment, a system includes a DAC that receives a multi-bit digital signal, generates at least two analog signals each indicative of the value of the multi-bit digital signal, and filters two or more of the at least two analog signals. In another embodiment, a system includes a DAC that receives digital input signals at an input data rate and outputs analog signals indicative of the digital signals to a signal conditioning stage at an output data rate different than the input data rate.

Claims

1. A DAC comprising:

a switched capacitor network that receives a multi-bit digital signal, the switched capacitor network having a plurality of sub DACs that each receive an associated bit of the multi-bit digital signal, each of the plurality of sub DACs having an associated capacitance that receives an associated amount of charge in response to the associated bit, wherein the associated amount of charge for each of the plurality of sub DACs is in direct proportion to a weight of the bit, the DAC having a charge sharing operating state in which at least two of the plurality of sub DACs share charge with one another, and having an operating state, initiated subsequent to the charge sharing operating state, in which the switched capacitor network outputs at least one analog signal indicative of a sum of values of each bit in the multi-bit signal.

2. The DAC of claim 1, wherein the multi-bit digital signal is an equally-weighted multi-bit digital signal, and the associated amount of charge is the same for each of the plurality of sub DACs.

3. The DAC of claim 1, wherein the multi-bit digital signal is an equally-weighted multi-bit digital signal, and the associated capacitance is the same for each of the plurality of sub DACs.

4. The DAC of claim 1, wherein each of the plurality of sub DACs shares charge with one another, and the switched capacitor network outputs an analog signal indicative of a sum of values of each bit in the multi-bit signal.

5. The DAC of claim 1, wherein the DAC comprises a plurality of switched capacitor cells used in forming the switched capacitor network, each of at least two of the plurality of switched capacitor cells has a orientation direction, and the at least two of the plurality of switched capacitor cells are oriented such that the orientation direction of at least one of the at least two of the plurality of switched capacitor cells is angularly offset relative to the orientation direction of at least one other of the at least two of the plurality of switched capacitor cells, the angular offset being substantially, ninety degrees.

6. The DAC of claim 1, wherein the DAC comprises a plurality of switched capacitor cells used in forming the switched capacitor network, each of at least four of the plurality of switched capacitor cells has a orientation direction, and the orientation direction of each one of the at least four of the plurality of switched capacitor cells is angularly offset relative to the orientation directions of the others of the at least four of the plurality of switched capacitor cells.

7. The system of claim 1 wherein the first analog signal and the second analog signal are substantially equal to each other.

8. The system of claim 1 wherein the first analog signal and the second analog signal are not substantially equal to each other.

9. The system of claim 1 wherein each of the at least two analog signals is indicative of a sum of values of all of the bits in the multi-bit digital signal.

10. The system of claim 1, wherein the at least two analog signals are not all substantially equal to each other.

11. The system of claim 1 wherein the signal conditioning stage generates a signal that is responsive to each of the at least two of the at least two analog signals.

12. The DAC of claim 1 wherein each of the plurality of sub DACs shares charge with at least one other of the plurality of sub DACs to generate at least one analog signal indicative of a sum of values of each bit in the multi-bit signal.

13. The DAC of claim 1 wherein the switched capacitor network generates the at least one analog signal in response to the charge received by the capacitance of each of the plurality of sub DACs in response to the associated bit.

14. The DAC of claim 1 wherein the DAC has more than one charge sharing operating state in which at least two of the plurality of sub DACs share charge with one another.

15. The DAC of claim 1 wherein the DAC has more than one operating state, subsequent to the charge sharing operating state, in which the switched capacitor network outputs at least one analog signal indicative of a sum of values of each bit in the multi-bit signal.

16. The DAC of claim 1, wherein for each of the plurality of sub DACs, the associated capacitance comprises a single capacitor.

17. The system of claim 16 wherein the signal conditioning stage comprises a switched capacitor filter stage.

18. The system of claim 16 wherein the signal conditioning stage generates a signal responsive in the sequence of analog signals.

19. The system of claim 16 wherein the DAC receives one digital input signal per operating cycle and the analog signals are output at a non periodic rate over the operating cycle.

20. A DAC comprising:

a switched capacitor network that receives an equally-weighted multi-bit digital signal, the switched capacitor network having a plurality of sub DACs, at least two of the plurality of sub DACs sharing charge with one another, wherein the switched capacitor network outputs an analog signal indicative of a sum of equally-weighted values of each bit in the multi-bit signal.

21. The DAC of claim 20, wherein the DAC comprises a plurality of switched capacitor cells used in forming the switched capacitor network, each of at least two of the plurality of switched capacitor cells has a orientation direction, and the at least two of the plurality of switched capacitor cells are oriented such that the orientation direction of at least one of the at least two of the plurality of switched capacitor cells is angularly offset relative to the orientation direction of at least one other of the at least two of the plurality of switched capacitor cells.

22. The DAC of claim 20, wherein the DAC comprises a plurality of switched capacitor cells used in forming the switched capacitor network, each of the at least four of the plurality of switched capacitor cells has an orientation direction, and the orientation direction of each one of the at least four of the plurality of switched capacitor cells is angularly offset relative to the orientation directions of the others of the at least four of the plurality of switched capacitor cells.

23. The DAC of claim 20 wherein each of the plurality of sub DACs shares charge with at least one other of the plurality of sub DACs to generate at least one analog signal indication of a sum of values of each bit in the multi-bit signal.

24. The DAC of claim 20 wherein the switched capacitor network generates the at least one analog signal in response to the charge received by the capacitance of each of the plurality of sub DACs in response to the associated bit.

25. The DAC of claim 21 wherein the angular offset is substantially ninety degrees.

27. The DAC of claim 20, wherein for each of the plurality of sub DACs, the associated capacitance comprises a single capacitor.

28. The method of claim 27 wherein the at least two analog signals are substantially equal to one another.

26. A DAC comprising:

a switched capacitor network that receives an equally-weighted multi-bit digital signal and outputs one or more analog signals, where at least one of the one or more analog signals comprises a single packet of charge indicative of a sum of equally-weighted values of each bit in the multi-bit signal.

29. A method of converting a multi-bit digital signal to an analog signal indicative of a sum of value of each bit in the multi-bit digital signal comprising:

charging each of a plurality of capacitors to a valve corresponding to a value of a bit in the multi-bit signal, wherein the charge on each capacitor corresponds to a weight of the value of a corresponding bit;

temporarily connecting at least two of the plurality of capacitors to one another to share charge; and

providing at least one analog output signal indicative of a sum of values of each bit in the multi-bit signal, after disconnecting the at least two of the plurality of capacitors from one another.

30. The system of claim 29 wherein the at least two analog signals are substantially equal to one another.

31. The method of claim 29, wherein the method further comprises connecting all of the capacitors together so each has substantially the same value.

32. The system of claim 29 wherein the means for generating comprises a switched capacitor DAC.

33. The method of claim 29 further comprising generating at least one analog signal indicative of a sum of the values of the bits in the multi-bit digital signal in response to the cahrge stored on each of the plurality of capacitors by the step of charging.

34. The method of claim 29 wherein connecting comprises connecting each of the plurality of sub DACs with at least one other of the plurality of sub DACs to share charge and generate at least one analog signal indicative of a sum of the values of the bits in the multi-bit digital signal.

35. A method of converting a equally-weighted multi-bit digital signal to an analog signal indicative of a sum of value of each bit in the multi-bit digital signal comprising:

charging each of a plurality of capacitors in a value corresponding to a value of a bit in the equally-weighted multi-bit signal, and

generating a single packet of charge on at least one capacitor indicative of a sum of equally-weighted values of each bit in the multi-bit signal.

36. A method of converting an equally weighted multi-bit digital signal to an analog signal indicative of a sum of value of each bit in the multi-bit digital signal comprising:

charging each of a plurality of capacitors to a value corresponding to a value of a bit in the equally-weighted multi-bit signal, and

connecting at least two of the plurality of capacitors to one another to share charge.

37. The method of claim 36 further comprising generating at least one analog signal indicative of a sum of the values of the bits in the multi-bit digital signal in response to the cahrge stored on each of the plurality of capacitors by the step of charging.

38. The method of claim 36 wherein connecting comprises connecting each of the plurality of sub DACs with at least one other of the plurality of sub DACs to share charge and generate at least one analog signal indicative of a sum of the values of the bits in the multi-bit digital signal.

39. A DAC comprising:

means for charging each of a plurality of capacitors to a value corresponding to a value of a bit in a multi-bit signal, wherein the charge on each capacitor corresponds to a weight of the value of a corresponding bit;

means for temporarily connecting at least two of the plurality of capacitors to one another to share charge; and

means for providing at least one analog output signal indicative of a sum of values of each bit in the multi-bit signal, after disconnecting the at least two of the plurality of capacitors from one another.

40. The DAC of claim 39 further comprising means for generating at least one analog signal indicative of a sum of the values of the bits in the multi-bit digital signal in response to the charge stored on each of the plurality of capacitors by the step of charging.

41. The DAC of claim 39 wherein means for connecting comprises means for connecting each of the plurality of sub DACs with at least one other of the plurality of sub DACs to share charge and generate at least one analog signal indicative of a sum of the values of the bits in the multi-bit digital signal.

42. A method comprising:

receiving a multi-bit digital signal;

generating at least two analog signals including a first analog signal that is indicative of a sum of values of bits in the multi-bit digital signal, and a second analog signal that is indicative of said sum of values of said bits in the multi-bit digital signal; and

providing at least two of the at least two analog signals to a signal conditioning stage, the at least two of the at least two analog signals including the first analog signal and the second analog signal.

43. The method of claim 42 wherein the first analog signal and the second analog signal are each indicative of a sum of values of all of the bits in the multi-bit digital signal.

44. The method of claim 42 wherein the first analog signal and the second analog signal are not substantially equal to each other.

45. The method of claim 42 wherein the at least two analog signals are each indicative of said sum of values of said bits in the multi-bit digital signal.

46. The method of claim 42 wherein the at least two analog signals are substantially equal to each other.

47. The method of claim 42 wherein the at least two analog signals are not substantially equal to each other.

48. A DAC comprising:

means for charging each of a plurality of capacitors to a value corresponding to a value of a bit in an equally-weighted multi-bit signal, and

means for generating a single packet of charge on at least one capacitor indicative of a sum of equally-weighted values of each bit in the multi-bit signal.

49. A DAC comprising:

means for charging each of a plurality of capacitors to a value corresponding to a value of a bit in an equally-weighted multi-bit signal, and

means for connecting at least two of the plurality of capacitors to one another to share charge.

50. The DAC of claim 49 further comprising means for generating at least one analog signal indicative of a sum of the values of the bits in the multi-bit digital signal in response to the charge stored on each of the plurality of capacitors by the step of charging.

51. The DAC of claim 49 wherein means for connecting comprises means for connecting each of the plurality of sub DACs with at least one other of the plurality of sub DACs to share charge and generate at least one analog signal indicative of a sum of the values of the bits in the multi-bit digital signal.

52. An integrated circuit comprising:

an integrated switched capacitor network that receives a multi-bit digital signal, the switched capacitor network having a plurality of sub DACs that each receive an associated bit of the multi-bit digital signal, each of the plurality of sub DACs having an associated capacitance that receives an associated amount of charge in response to the associated bit, wherein the associated amount of charge for each of the plurality of sub DACs is in direct proportion to a weight of the bit, the integrated switched capacitor network having a charge sharing operating state in which at least two of the plurality of sub DACs share charge with one another, and

having an operating state, initiated subsequent to the charge sharing operating state, in which the switched capacitor network outputs at least one analog signal indicative of a sum of values of each bit in the multi-bit signal.

53. The DAC of claim 52 wherein each of the plurality of sub DAC shares charge with at least one other of the plurality of sub DACs to generate at least one analog signal indicative of a sum of values of each bit in the multi-bit signal.

54. The DAC of claim 52 wherein the switched capacitor network generates the at least one analog signal in response to the charge received by the capacitance of each of the plurality of sub DACs in response to the associated bit.

55. An integrated circuit comprising:

an integrated switched capacitor network that receives an equally-weighted multi-bit digital signal and outputs one or more analog signals, wherein at least one of the one or more analog signals comprises a single packet of charge indicative of a sum of equally-weighted values of each bit in the multi-bit signal.

56. An integrated circuit comprising:

an integrated switched capacitor network that receives an equally-weighted multi-bit digital signal, the switched capacitor network having a plurality of sub DACs, at least two of the plurality of sub DACs sharing charge with one another, wherein the switched capacitor network outputs an analog signal indicative of a sum of equally-weighted values of each bit in the multi-bit signal.

57. The DAC of claim 56 wherein each of the plurality of sub DACs shares charge with at least one other of the plurality of sub DACs to generate at least one analog signal indicative of a sum of values of each bit in the multi-bit signal.

58. The DAC of claim 56 wherein the switched capacitor network generates the at least one analog signal in response to the charge received by the capacitance of each of the plurality of sub DACs in response to the associated bit.

59. A DAC comprising:

a switched capacitor network that receives a multi-bit digital signal, the switched capacitor network having a plurality of sub DACs that each receive an associated bit of the multi-bit digital signal, each of the plurality of sub DACs having an associated capacitance that receives an associated amount of charge in response to the associate bit, wherein the associated amount of charge for each of the plurality of sub DACs is in direct proportion to a weight of the bit, the DAC having an operating state in which at least two of the plurality of sub DACs share charge with one another, and having an operating state in which fewer than all of the plurality of sub DACs are connected to an output terminal and the switched capacitor network outputs at least one analog signal indicative of a sum of values of each bit in the multi-bit signal.

60. The DAC of claim 59 wherein the DAC has more than one charge sharing operating state in which at least two of the plurality of sub DACs share charge with one another.

61. The DAC of claim 59 wherein the DAC has more than one operating state in which fewer than all of the plurality of sub DACs are connected to an output terminal and the switched capacitor network outputs at least one analog signal indicative of a sum of values of each bit in the multi-bit signal.

62. The DAC of claim 59 wherein in the operating state in which fewer than all of the plurality of sub DACs are connected to an output terminal and the switched capacitor network outputs at least one analog signal indicative of a sum of values of each bit in the multi-bit signal, the sub DACs that are connected to the output terminal deliver charge to said output terminal.

63. A method of converting a multi-bit digital signal to an analog signal indicative of a sum of value of each bit in the multi-bit digital signal comprising the steps of:

charging each of a plurality of capacitors to a value corresponding to a value of a bit in the multi-bit signal, wherein the charge on each capacitor corresponds to a weight of the value of a corresponding bit;

connecting at least two of the plurality of capacitors to one another to share the charge; and

connecting fewer than all of the plurality of sub DACs to an output terminal to provide at least one analog output signal indicative of a sum of values of each bit in the multi-bit signal.

64. A DAC comprising:

means for charging each of a plurality of capacitors to a value corresponding to a value of a bit in a multi-bit signal, wherein the charge on each capacitor corresponds to a weight of the value of a corresponding bit;

means for connecting at least two of the plurality of capacitors to one another to share charge; and

means for connecting fewer than all of the plurality sub DACs to an output terminal to provide at least one analog output signal indicative of a sum of values of each bit in the multi-bit signal.

65. An integrated circuit comprising:

an integrated switched capacitor network that receives a multi-bit digital signal, the switched capacitor network having a plurality of sub DACs that each receive an associated bit of the multi-bit digital signal, each of the plurality of sub DACs having an associated capacitance that receives an associated amount of charge in response to the associated bit, wherein the associated amount of charge for each of the plurality of sub DACs is in direct proportion to a weight of the bit, the integrated switched capacitor network having an operating state in which at least two of the plurality of sub DACs share cahrge with one another, and having an operating state in which fewer than all of the plurality of sub DACs are connected to an output terminal and the switched capacitor network outputs at least one analog signal indicative of a sum of values of each bit in the multi-bit signal.