System and method for aligning multi-channel coded data over multiple clock periods

• US 6,917,366 B1
• Filed: 04/04/2001
• Issued: 07/12/2005
• Est. Priority Date: 04/04/2000
• Status: Expired due to Term

• Current Assignee: Pixelworks Semiconductor Technology Company Limited
• Original Assignee: Pixelworks Incorporated
• Inventors: West, Michael G., LeVasseur, Jamie J.
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): NGUYEN, HAU H
• Application Number:
  US09/826,538
• Time in Patent Office: 1,560 Days
• Field of Search: 365/556, 365/559, 365/505, 365/99, 375/366, 375/355, 370/537, 345/558, 345/547, 345/213, 345/530, 710/22, 710/29
• US Class Current: 345/558
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Abstract

A system and method is provided for aligning multi-channel coded data over multiple clock periods. Data is received through a plurality of data channels and stored in a plurality of latches or queues. Data is scanned to determine whether a valid data transition has occurred. Once a valid transition is detected on all of the plurality of data channels, data is substantially simultaneously read out of the latches or queues resulting in synchronized or aligned data being provided at the output.

Claims

1. A system to align digital image data, comprising:

a plurality of serial data channels, each channel transmitting corresponding serial data, the serial data on one serial channel having skew relative to the serial data on other serial channels;

a serial to parallel converter to convert the serial data on each of the plurality of serial data channels into parallel data on corresponding parallel data channels responsive to a serial reference clock; and

an alignment circuit adapted to align the parallel data such that no skew is present between the parallel data on one parallel channel and the parallel data on other parallel channels responsive to a pixel clock;

wherein the serial to parallel converter generates a pixel clock for each parallel data channel and a parallel reference clock;

wherein the alignment circuit comprises;

a queue circuit to store the parallel data on each of the parallel data channels responsive to the corresponding pixel clock; and

an alignment detection circuit to detect alignment of the parallel data stored in the queue circuit responsive to the parallel reference clock; and

wherein the queue circuit for each of the parallel data channels comprises;

a plurality of FIFO latches, each FIFO latch to store parallel data responsive to the corresponding pixel clock;

a compare circuit to generate a match bit for each word of parallel data by monitoring the parallel data for a code;

a register circuit to generate a leading edge signal responsive to the corresponding pixel clock;

a counter circuit to generate a write pointer responsive to the corresponding pixel clock;

a latch circuit to generate a leading edge pointer by latching the write pointer responsive to the leading edge signal and the corresponding pixel clock; and

a multiplexer circuit to receive parallel data stored in the plurality of FIFO latches and output aligned parallel data to a corresponding parallel data channel responsive to a corresponding read pointer.

2. The system of claim 1

wherein each FIFO latch stores a word of parallel data responsive to an enable signal;

and

wherein the counter circuit generates the enable signal responsive to the corresponding pixel clock.

3. The system of claim 2 wherein the counter circuit generates the enable signal further responsive to a reset signal.

4. The system of claim 1 wherein the code is a blanking code.

5. The system of claim 1 wherein the register circuit generates the leading edge signal by comparing a match bit for a presently stored word of parallel data with a match bit for a previously stored word of parallel data.

6. The system of claim 1 wherein the alignment detection circuit comprises:

an alignment detection block for each of the parallel data channels, each block to generate the corresponding read pointer responsive to the parallel reference clock; and

a synchronization circuit to receive a leading edge detect signal from each of the alignment detection blocks for each of the parallel data channels and generate a reload read pointer responsive to the parallel reference clock.

7. The system of claim 6 wherein each alignment detection block comprises:

a shift circuit to receive the corresponding leading edge pointer and generate the corresponding read pointer responsive to the reload read pointer;

a latch to receive the leading edge signal and generate a leading edge detect signal for the corresponding parallel data channel responsive to the reload read pointer.

8. The system of claim 7 wherein the shift circuit comprises:

a first multiplexer to select between the corresponding leading edge pointer and corresponding read pointer responsive to the reload read pointer;

a shift register to generate a shifted signal by shifting a first multiplexer output signal; and

a second multiplexer to select between the first multiplexer output signal and the shifted output signal responsive to the reload read pointer.

9. The system of claim 1 further comprising a decoder adapted to receive the aligned parallel data on corresponding parallel channels from the alignment circuit, the decoder meeting the digital visual interface specification version 1.0.

10. An alignment circuit receiving input parallel data on a plurality of input parallel data channels and generating output parallel data transmissible on a plurality of output parallel data channels, the input parallel data on one input parallel data channel having skew relative to the input parallel data on other input parallel data channels, comprising:

an alignment detection circuit to generate a plurality of read pointers corresponding to the plurality of input parallel data channels responsive to a parallel reference clock signal; and

a plurality of FIFO circuits corresponding to the plurality of input parallel data channels to generate the output parallel data responsive to the plurality of read pointers;

wherein the output data on one output channel has no skew relative to the output data on other output channels;

wherein the alignment detection circuit comprises an alignment detection block for each input data channel, each alignment detection block to generate a read pointer for each input data channel responsive to the parallel reference clock;

wherein each alignment detection block comprises;

a read pointer generating circuit to receive a corresponding leading edge pointer and generate the corresponding read pointer responsive to a reload read pointer signal; and

a latch to receive a leading edge signal and generate a leading edge detect signal for the corresponding input data channel responsive to the reload read pointer signal.

11. The alignment circuit of claim 10

wherein the read pointer generating circuit comprises:

a first multiplexer to multiplex between the corresponding leading edge pointer and corresponding read pointer responsive to the reload read pointer;

a shift circuit to generate a shifted signal by shifting a first multiplexer output signal; and

a second multiplexer to multiplex between the first multiplexer output signal and the shifted output signal responsive to the reload read pointer.

12. The alignment circuit of claim 10 wherein the alignment detection circuit further comprises a feedback circuit to generate the reload read pointer signal responsive to the parallel reference clock.

13. The alignment circuit of claim 12 wherein the feedback circuit comprises:

a logic gate to generate a logic gate signal by logically manipulating leading edge detect signals from each input data channel;

a plurality of serially connected registers to generate the reload read pointer signal by registering the logic gate signal responsive to the parallel reference clock.

14. An alignment circuit receiving input parallel data on a plurality of input parallel data channels and generating output parallel data transmissible on a plurality of output parallel data channels, the input parallel data on one input parallel data channel having skew relative to the input parallel data on other input parallel data channels, comprising:

an alignment detection circuit to generate a plurality of read pointers corresponding to the plurality of input parallel data channels responsive to a parallel reference clock signal; and

a plurality of FIFO circuits corresponding to the plurality of input parallel data channels to generate the output parallel data responsive to the plurality of read pointers;

wherein the output data on one output channel has no skew relative to the output data on other output channels;

wherein each FIFO circuit comprises;

a plurality of FIFO latches, each FIFO latch to store a word of input data responsive to a corresponding pixel clock;

a compare circuit to generate a match bit for each word of input data by monitoring the input data for a code;

a register circuit to generate a leading edge signal responsive to the corresponding pixel clock;

a counter circuit to generate a write pointer responsive to the corresponding pixel clock;

a latch circuit to generate a leading edge pointer by latching the write pointer responsive to the leading edge signal and the corresponding pixel clock; and

a multiplexer circuit to receive input data stored in the plurality of FIFO latches and output aligned input data to a corresponding input data channel responsive to a corresponding read pointer.

15. The alignment circuit of claim 14 wherein the code is a DVI blanking code.

16. The alignment circuit of claim 14 wherein the counter circuit generates an enable signal responsive to the corresponding pixel clock and a reset signal and wherein each FIFO latch is enabled by the enable signal.

17. The alignment circuit of claim 14 wherein the logic circuit generates the leading edge signal by logically manipulating the match bit of a presently stored data word with a match bit of a previously stored data word responsive to corresponding pixel clock.

18. A method for aligning parallel image data, comprising:

receiving the data on a plurality of channels, the data on one channel having skew relative to the data on another channel;

storing the data in a plurality of queues;

detecting a valid data transition by checking the data for a predetermined code;

setting a read pointer for each channel responsive to the valid data transition; and

aligning the data by reading the plurality of queues once the read pointers for each of the channels point to a valid data transition;

wherein detecting a valid data transition comprises scanning each word of data for the code; and

wherein detecting a valid data transition comprises;

storing the code for a previous word of data;

storing the code for a present word of data; and

comparing the code for the previous with the code for the present word of data.

19. The method of claim 18 wherein receiving the data comprises:

receiving serial data on a plurality of serial channels;

converting the serial data to parallel data; and

providing the parallel data to a plurality of parallel channels.

20. The method of claim 18 wherein storing the data in a plurality of queues includes for each channel storing a word of data in a plurality of FIFO latches responsive to a corresponding pixel clock.

21. The method of claim 18 wherein detecting a valid data transition includes generating a leading edge signal as a result of comparing the code.

22. The method of claim 21 wherein detecting a valid data transition includes:

generating a write pointer responsive to the pixel clock; and

generating a leading edge pointer by latching the write pointer responsive to the leading edge signal and the pixel clock.

23. The method of claim 22 wherein setting the read pointer includes:

generating a reload read pointer by logically manipulating the leading edge signal from each data channel; and

latching the leading edge pointer responsive to the reload read pointer.

24. The method of claim 23 wherein aligning the data by reading the plurality of queues includes:

multiplexing data from the plurality of FIFO latches to a corresponding data channel responsive to the read pointer, wherein multiplexed data provided to one data channel is aligned relative to other multiplexed data provided to other data channels.