Semiconductor integrated circuit having unit cells
First Claim
1. A semiconductor integrated circuit comprising:
- a unit cell array including a plurality of logic unit cells for providing general circuits and a plurality of clock unit cells for providing clock drivers;
a power trunk line formed on a peripheral area of the unit cell array, the power trunk line supplying a power source potential;
a plurality of first power branch lines formed on the unit cell array for supplying the power source potential to the logic unit cells, the first power branch lines connected each other and connected to the power trunk line; and
a plurality of second power branch lines formed on the unit cell array for supplying the power source potential to the clock unit cells, the second power branch lines connected each other and connected to the power trunk line.
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Accused Products
Abstract
A semiconductor integrated circuit includes a unit cell array, a power trunk line, first power branch lines and second power branch lines. The unit cell array includes logic unit cells for providing general circuits and clock unit cells for providing clock drivers. The power trunk line is formed on a peripheral area of the unit cell array. The power trunk line supplies a power source potential. The first power branch lines are formed on the unit cell array for supplying the power source potential to the logic unit cells. The first power branch lines are connected each other and connected to the power trunk line. The second power branch lines are formed on the unit cell array for supplying the power source potential to the clock unit cells. The second power branch lines are connected each other and connected to the power trunk line.
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Citations
21 Claims
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1. A semiconductor integrated circuit comprising:
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a unit cell array including a plurality of logic unit cells for providing general circuits and a plurality of clock unit cells for providing clock drivers;
a power trunk line formed on a peripheral area of the unit cell array, the power trunk line supplying a power source potential;
a plurality of first power branch lines formed on the unit cell array for supplying the power source potential to the logic unit cells, the first power branch lines connected each other and connected to the power trunk line; and
a plurality of second power branch lines formed on the unit cell array for supplying the power source potential to the clock unit cells, the second power branch lines connected each other and connected to the power trunk line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor integrated circuit comprising:
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a unit cell array including a plurality of logic unit cells for providing general circuits and a plurality of clock unit cells for providing clock drivers;
a first power trunk line formed on a peripheral area of the unit cell array, the first power trunk line supplying a power source potential;
a second power trunk line formed on the peripheral area, the second power trunk line supplying the power source potential, the first and second power trunk line being disconnected in the peripheral area;
a plurality of first power branch lines formed on the unit cell array for supplying the power source potential to the logic unit cells, the first power branch lines connected each other and connected to the first power trunk line; and
a plurality of second power branch lines formed on the unit cell array for supplying the power source potential to the clock unit cells, the second power branch lines connected each other and connected to the second power trunk line. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A semiconductor integrated circuit comprising:
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a unit cell block having a plurality of unit cells disposed in matrix form, the unit cell block having a plurality of logic unit cells for providing general circuit and a plurality of clock unit cells for providing clock drivers;
a first power branch line provided along a row direction of the matrix, the first power branch line supplying a source potential and a ground potential to the logic unit cells;
a second power branch line provided along the row direction, the second power branch line supplying the source potential and the ground potential to the clock unit cells; and
a power trunk line connected to ends of the first power branch line and the second power branch line. - View Dependent Claims (18, 19, 20, 21)
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Specification