Channel reassignment method and circuit for implementing the same

• US 6,917,584 B2
• Filed: 03/16/2001
• Issued: 07/12/2005
• Est. Priority Date: 09/22/2000
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kuwabara, Takashi
• Primary Examiner(s): Sam, Phirin
• Application Number:
  US09/810,240
• Publication Number:
  US 20020057679A1
• Time in Patent Office: 1,579 Days
• Field of Search: 370/215, 370/216, 370/217, 370/218, 370/219, 370/220, 370/225, 370/227, 370/228, 370/242, 370/244, 370/247, 370/248, 370/250, 370/251, 370/252, 370/253, 370/401, 370/402, 370/403, 370/431, 370/433, 370/437, 370/468, 370/222, 370/223, 370/224, 370/404, 370/405, 370/406
• US Class Current: 370/225
• CPC Class Codes: H04J 2203/0042 Ring
• CPC Class Codes: H04J 2203/006 Fault tolerance and recovery
• CPC Class Codes: H04J 2203/0069 Channel allocation
• CPC Class Codes: H04J 3/0623 Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
• CPC Class Codes: H04J 3/076 Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
• CPC Class Codes: H04J 3/085 for ring networks, e.g. SDH/SONET rings, self-healing rings, meashed SDH/SONET networks

Abstract

A channel reassignment is accomplished without causing a momentary interruption resulting from a mismatch in pointer value. After a bridge setting is made between a source channel and destination channel at a first node designated as the starting point of a reassignment section, messages B/C are sent out from the first node toward a fourth node designated as the end point. Second and third nodes that received the message C each transfer the message to the next node after interlinking the pointer operation of the destination channel with the source channel. The fourth node that received the message C sends out a message D toward the first node after changing the setting of a TSA. The second and third nodes that received the message D transfers the message to the next node after clearing the pointer interlinking operation.

Claims

1. A channel reassignment method comprising the steps of:

(a) at a starting point of a reassignment section, making a bridge setting for transmitting a signal on a source channel also onto a destination channel;

(b) interlinking a pointer operation of a first pointer circuit in said destination channel with a pointer operation of a second pointer circuit in said source channel;

(c) switching the signal from the source channel to the destination channel after performing steps (a) and (b);

(d) clearing the pointer interlinking operation effected in step (b) after performing step (c); and

(e) clearing the bridge setting made in step (a) after performing step (c).

5. A method according to claim 1, wherein steps (a), (b), (c), (d), and (e) are performed on both a working channel and a protection channel in parallel fashion.

2. A channel reassignment method comprising the steps of:

(a) at a starting point of a reassignment section, making a bridge setting for transmitting a signal on a source channel also onto a destination channel;

(b) interlinking the pointer operation of said destination channel with said source channel in all pointer circuits located along said reassignment section;

(c) switching the signal from the source channel to the destination channel after performing steps (a) and (b);

(d) clearing the pointer interlinking operation effected in step (b) after performing step (c); and

(e) clearing the bridge setting made in step (a) after performing step (c);

and further comprising the steps of;

sending a first message to an end point of the reassignment section from the starting point; and

sending a second message from the end point to the starting point in response to the first message, and wherein;

step (b) is performed by being triggered by the first message, and

step (d) is performed by being triggered by the second message.

3. A method according to claim 2, wherein

step (b) is performed at each point located along the reassignment section, step (b) comprising the substeps of:

(i) initiating the pointer interlinking operation upon reception of the first message; and

(ii) transferring the first message after initiating the pointer interlinking operation, and

step (d) is performed at each point located along the reassignment section, step (d) comprising the substeps of;

(i) clearing the pointer interlinking operation upon reception of the second message; and

(ii) transferring the second message after clearing the pointer interlinking operation.

4. A method according to claim 2, wherein step (c) is performed at each point located along the reassignment section by being triggered by the second message.

6. A pointer circuit for performing pointer processing between receiving and transmitting ends of a plurality of channels, the pointer circuit comprising for each channel:

an ES memory temporarily storing payload data of each channel;

a phase comparator generating a stuff request by comparing a write address and read address for the ES memory; and

a pointer determining unit determining a pointer at the transmitting end based on the stuff request, wherein

the pointer circuit further comprises for each channel;

first and second selectors selecting, for a destination channel, a write address and a read address of a source channel as the write address and the read address for the ES memory at the time of channel reassignment, and supplying the selected write address and read address to the ES memory; and

a third selector selecting, for the destination channel, a stuff request of the source channel as the stuff request, and supplying the selected stuff request to the pointer determining unit.

7. A pointer processing circuit according to claim 6, wherein

the first and second selectors further select, for each of concatenated channels, a write address and a read address of a leading channel of the concatenated channel as the write address and read address, and

selects, for each of concatenated destination channels, the write address and read address of a leading channel of the concatenated destination channel as the write address and read address for the ES memory.