Method, architecture and circuitry for controlling pulse width in a phase and/or frequency detector

• US 6,917,661 B1
• Filed: 09/24/1999
• Issued: 07/12/2005
• Est. Priority Date: 09/24/1999
• Status: Expired due to Term

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Raza, S. Babar, Scott, Paul H.
• Primary Examiner(s): BURD, KEVIN MICHAEL
• Application Number:
  US09/404,891
• Time in Patent Office: 2,118 Days
• Field of Search: 375/375, 375/372, 375/376, 375/362, 375/354, 375/327, 375/316, 375/373, 375/219, 375/220, 375/221
• US Class Current: 375/375
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 7/0079 Receiver details
• CPC Class Codes: H04L 7/0091 Transmitter details
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a parallel output data signal in response to (i) a first clock signal and (ii) one or more serial data signals. The second circuit may be configured to present the one or more serial data signals and the first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal.

Claims

1. An apparatus comprising:

a first circuit configured to present a parallel output data signal in response to (i) a selected phase of a plurality of phases of a first multi-phased clock signal and (ii) two or more serial data signals; and

a second circuit configured to present said two or more serial data signals and said first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal.

2. The apparatus according to claim 1, wherein said first multi-phased clock signal comprises a bit clock signal.

3. The apparatus according to claim 1, wherein said second clock signal comprises a reference clock signal.

4. The apparatus according to claim 1, wherein said selected phase of said multi-phased first clock signal is selected in response to a phase selection circuit.

5. The apparatus according to claim 1, wherein:

a phase generation circuit is configured to generate said plurality of phases of said first clock signal.

6. The apparatus according to claim 1, wherein said first circuit further comprises:

a third circuit configured to generate (i) one or more select signals and (ii) a selected clock signal in response to (i) said first multi-phased clock signal and (ii) a phase select signal.

7. The apparatus according to claim 6, wherein said third circuit comprises a phase generation and select circuit.

8. The apparatus according to claim 6, wherein said first circuit further comprises:

a phase comparator circuit configured to generate said phase select signal in response to said one or more select signals and a first of said two or more serial data signals.

9. The apparatus according to claim 8, wherein said first circuit includes a deserializer circuit configured to generate said parallel output data signal in response to said selected clock signal and a second of said two or more serial data signals.

10. The apparatus according to claim 9, wherein said first circuit further comprises:

a multiplexer configured to generate (i) said first of said two or more serial data signals and (ii) said second of said two or more serial data signals, in response to said two or more serial data signals.

11. A circuit comprising:

means for generating a parallel output data signal in response to (i) a selected phase a plurality of phases of a multi-phased first clock signal and (ii) two or more serial data signals; and

means for generating said two or more serial data signals and said multi-phased first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal.

12. A method for controlling a pulse width in a phase and/or frequency detector comprising the steps of:

(A) generating a parallel output data signal in response to (i) a selected phase of a plurality of phases of a multi-phased first clock signal and (ii) two or more serial data signals; and

(B) generating said two or more serial data signals and said first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal, wherein said multi-phased first clock signal is configured to control said pulse width.

13. The method according to claim 12, wherein said multi-phased first clock signal comprises a bit clock signal.

14. The method according to claim 12, wherein said second clock signal comprises a reference clock signal.

15. The method according to claim 12, wherein step (A) further comprises the sub-step of:

generating (i) one or more select signals and (ii) a selected clock signal in response to (i) said first clock signal and (ii) a phase select signal.

16. The method according to claim 15, wherein step (A) further comprises the sub-step of:

generating said phase select signal in response to said one or more select signals and a first of said two or more serial data signals.

17. The method according to claim 16, wherein step (A) further comprises the sub-step of:

generating said parallel output data signal in response to said selected clock signal and a second of said two or more serial data signals.

18. The method according to claim 17, further comprising the step of:

generating said first of said two or more serial data signals and said second of said two or more serial data signals, in response to said two or more serial data signals.

19. An apparatus comprising:

a first circuit configured to present a parallel output data signal in response to (i) a selected phase of a first clock signal and (ii) two or more serial data signals;

a second circuit configured to present said two or more serial data signals and said first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal; and

a third circuit configured to generate (i) one or more select signals and (ii) a selected clock signal in response to (i) said first clock signal and (ii) a phase select signal.