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System and method for in-system programming through an on-system JTAG bridge of programmable logic devices on multiple circuit boards of a system

  • US 6,918,027 B2
  • Filed: 07/30/2001
  • Issued: 07/12/2005
  • Est. Priority Date: 07/30/2001
  • Status: Expired due to Term
First Claim
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1. A system comprising:

  • a plurality of programmable logic devices, including at least a first and a second programmable logic device, the first and second programmable logic devices coupled to receive programmable logic device configuration code from a first and a second EEPROM associated therewith;

    a first serial bus coupling the first EEPROM with a common configuration logic, and a second serial bus coupling the second EEPROM with the common configuration logic;

    a processor coupled to the common configuration logic, wherein the processor is also coupled to a memory subsystem;

    wherein the processor is capable of transferring programmable logic configuration code from its memory subsystem into the first EEPROM;

    wherein the first &

    second EEPROM are located on separate PC boards of the system;

    wherein the processor is coupled to the common configuration logic through a third serial bus;

    wherein the programmable logic devices are field programmable gate arrays; and

    wherein at least one EEPROM is located on the same integrated circuit as a field programmable gate array.

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