Random code generation using genetic algorithms
First Claim
1. In a system including a circuit design and a plurality of circuit input vectors which have been applied to the circuit design to produce at least one occurrence of each of a plurality of events within the circuit design, a method comprising:
- (A) identifying a plurality of counter values indicating a number of occurrences of each of the plurality of events;
(B) initializing an aggregate fitness value; and
(C) performing the following for each event e in the plurality of events;
(C) (1) identifying a counter value indicating a number of occurrences of event e;
(C) (2) applying a counter fitness function to the counter value identified in (C) (1) to produce a counter fitness value; and
(C) (3) applying a combination function to the aggregate fitness value and the counter fitness value to produce a new value for the aggregate fitness value.
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Accused Products
Abstract
Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability distribution of a plurality of microprocessor instructions. A random code generator takes the configuration file as an input and generates test instructions which are distributed according to the probability distribution specified by the knobs. The test instructions are executed on the microprocessor design. The microprocessor behaviors that are exercised by the test instructions are measured and a fitness value is assigned to the configuration file using a fitness function. The configuration file and its fitness value are added to a pool of configuration files. A configuration file synthesizer uses a genetic algorithm to synthesize a new configuration file from the pool of existing configuration files. This process may be repeated to generate configuration files which increasingly exercise microprocessor behaviors which are of interest.
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Citations
16 Claims
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1. In a system including a circuit design and a plurality of circuit input vectors which have been applied to the circuit design to produce at least one occurrence of each of a plurality of events within the circuit design, a method comprising:
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(A) identifying a plurality of counter values indicating a number of occurrences of each of the plurality of events;
(B) initializing an aggregate fitness value; and
(C) performing the following for each event e in the plurality of events;
(C) (1) identifying a counter value indicating a number of occurrences of event e;
(C) (2) applying a counter fitness function to the counter value identified in (C) (1) to produce a counter fitness value; and
(C) (3) applying a combination function to the aggregate fitness value and the counter fitness value to produce a new value for the aggregate fitness value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system comprising:
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a circuit design;
a plurality of circuit input vectors which have been applied to the circuit design to produce at least one occurrence of a plurality of events within the circuit design;
counter value identification means for identifying a plurality of counter values indicating a number of occurrences of each of the plurality of events;
means for initializing an aggregate fitness value; and
fitness calculation means for performing the following for each event e in the plurality of events;
(1) identifying a counter value indicating a number of occurrences of event e;
(2) applying a counter fitness function to the counter value identified in (1) to produce a counter fitness value; and
(3) applying a combination function to the aggregate fitness value and the counter fitness value to produce a new value for the aggregate fitness value. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification