Apparatus and methods for determining critical area of semiconductor design data

• US 6,918,101 B1
• Filed: 10/24/2002
• Issued: 07/12/2005
• Est. Priority Date: 10/25/2001
• Status: Expired due to Term

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Song, Li, Nurani, Raman K., Satya, Akella V.
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US10/281,416
• Time in Patent Office: 992 Days
• Field of Search: 716 4- 5, 700108-110, 700/121
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are mechanisms for efficiently and accurately calculating critical area. In general terms, a method for determining a critical area for a semiconductor design layout is disclosed. The critical area is utilizable to predict yield of a semiconductor device fabricated from such layout. A semiconductor design layout having a plurality of features is first provided. The features have a plurality of polygon shapes which include nonrectangular polygon shapes. Each feature shape has at least one attribute or artifact, such as a vertex or edge. A probability of fail function is calculated based on at least a distance between two feature shape attributes or artifacts. By way of example implementations, a distance between two neighboring feature edges (or vertices) or a distance between two feature edges (or vertices) of the same feature is first determined and then used to calculate the probability of fail function. In a specific aspect, the distances are first used to determine midlines between neighboring features or midlines within a same feature shape, and the midlines are then used to determine the probability of fail function. A critical area of the design layout is then determined based on the determined probability of fail function. In specific implementations, the defect type is a short type defect or an open type defect. In a preferred implementation, the features may have any suitable polygonal shape, as is typical in a design layout.

Claims

1. A method for determining a critical area of at least a portion of a design layout, the design layout comprising design shapes, the design shapes comprising design shapes artifacts, the method comprising:

dividing the design layout into a plurality of points;

for each point, determining a critical radius corresponding to at least one defect type, wherein the determination is based on a plurality of distances between the each point and one or more neighboring design shape artifacts, without iteratively changing defect size or dimensions of the design shapes;

for each point, defining a probability of fail function based upon the critical radius; and

for each point, defining the probability of fail function to be equal to zero when a radius of a defect is smaller than the critical radius; and

for each point, defining the probability of fail function to be equal to one when the radius of the defect is larger than the critical radius.

2. A method as recited in claim 1, wherein the neighboring design shape artifacts include a vertex and an edge.

3. A method as recited in claim 1, wherein the defect type is an open or short type defect.

4. A method as recited in claim 3, wherein the design shapes include nonrectangular shapes.

5. A method as recited in claim 1 further comprising:

determining the critical area based upon the probability of fail functions of each of the points and a defect size distribution.

6. A method for determining a critical area of at least a portion of a layout of a circuit pattern, the layout comprising a plurality of features having a plurality of attributes, the method comprising:

first, selecting two attributes from the plurality of features;

second, determining a critical radius of the critical area based on the selected two attributes; and

based on the critical radius, determining the critical area in a non-iterative manner,

wherein the operation of determining the critical area based upon the critical radius further comprises defining a probability of fail function based upon the critical radius, wherein for each point, the probability of fail function is defined to be equal to zero when a radius of a defect is smaller than the critical radius and defined to be equal to one when the radius of the defect is larger than the critical radius.

7. A method as recited in claim 6, wherein the selected two attributes include an edge and/or a vertex of one or more features.

8. A method as recited in claim 6, wherein a shape of the feature(s) having the two selected attributes is nonrectangular.