Circuit, apparatus, and method for converting analog signals into digital signals

• US 6,919,831 B1
• Filed: 04/28/2004
• Issued: 07/19/2005
• Est. Priority Date: 04/28/2004
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Tagare, Madhavi V.
• Primary Examiner(s): Jeanglaude, Jean Bruner
• Application Number:
  US10/833,500
• Time in Patent Office: 447 Days
• Field of Search: 341/143, 341/156, 341/159, 341/118, 341/131, 341/122, 178/18.06, 348/572, 330/9
• US Class Current: 341/122
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods

Abstract

An analog-to-digital converter includes a sample and hold tree having a first level and at least one additional level. Each level includes one or more sample and hold circuits operable to sample an input voltage and produce a corresponding output voltage. The input voltage sampled by the one or more sample and hold circuits in each additional level represents the output voltage from the one or more sample and hold circuits in a preceding level. The analog-to-digital converter also includes a plurality of comparators. Each comparator is operable to compare the output voltage from one of the sample and hold circuits with one of a plurality of reference voltages. In addition, the analog-to-digital converter includes a state machine operable to receive outputs from the comparators and generate a digital output value.

Claims

1. An analog-to-digital converter, comprising:

a sample and hold tree comprising a first level and at least one additional level, each level comprising one or more sample and hold circuits operable to sample an input voltage and produce a corresponding output voltage, wherein the input voltage sampled by the one or more sample and hold circuits in each additional level comprises the output voltage from the one or more sample and hold circuits in a preceding level;

a plurality of comparators, each comparator operable to compare the output voltage from one of the sample and hold circuits with one of a plurality of reference voltages; and

a state machine operable to receive outputs from the comparators and generate a digital output value.

2. The analog-to-digital converter of claim 1, wherein:

the first level of the sample and hold tree comprises a single sample and hold circuit; and

a first bit in the digital output value is based on the output of the comparator associated with the sample and hold circuit in the first level.

3. The analog-to-digital converter of claim 2, wherein:

the at least one additional level comprises a second level having two sample and hold circuits, wherein only one of the two sample and hold circuits samples the input voltage to produce the output voltage; and

a second bit in the digital output value is based on the output of the comparator associated with the sample and hold circuit in the second level that samples the input voltage.

4. The analog-to-digital converter of claim 3, wherein:

the at least one additional level further comprises a third level having four sample and hold circuits, wherein only one of the four sample and hold circuits samples the input voltage to produce the output voltage; and

a third bit in the digital output value is based on the output of the comparator associated with the sample and hold circuit in the third level that samples the input voltage.

5. The analog-to-digital converter of claim 1, wherein each additional level of the sample and hold tree comprises more sample and hold circuits than the preceding level of the sample and hold tree.

6. The analog-to-digital converter of claim 5, further comprising clock gating logic operable to receive an input clock signal and generate at least one additional clock signal;

and

wherein, based on the input clock signal and the at least one additional clock signal, only one sample and hold circuit in each level of the sample and hold tree samples the input voltage for each cycle of the input clock signal.

7. The analog-to-digital converter of claim 1, further comprising a reference voltage ladder operable to produce the plurality of reference voltages.

8. The analog-to-digital converter of claim 1, wherein the state machine comprises an encoder.

9. The analog-to-digital converter of claim 1, wherein:

the state machine produces an n-bit digital output value; and

the plurality of comparators comprises 2ⁿ−

1 comparators.

10. The analog-to-digital converter of claim 1, wherein the state machine is operable to resolve one bit of the digital output value for each cycle of an input clock signal.

11. An apparatus, comprising:

an interface operable to receive an incoming signal; and

an analog-to-digital converter comprising;

a sample and hold tree comprising a first level and at least one additional level, each level comprising one or more sample and hold circuits operable to sample an input voltage and produce a corresponding output voltage, wherein the input voltage sampled by the one or more sample and hold circuits in the first level comprises the incoming signal, and wherein the input voltage sampled by the one or more sample and hold circuits in each additional level comprises the output voltage from the one or more sample and hold circuits in a preceding level;

a plurality of comparators, each comparator operable to compare the output voltage from one of the sample and hold circuits with one of a plurality of reference voltages; and

a state machine operable to receive outputs from the comparators and generate a digital output value corresponding to the incoming signal.

12. The apparatus of claim 11, wherein:

the first level of the sample and hold tree comprises a single sample and hold circuit; and

a first bit in the digital output value is based on the output of the comparator associated with the sample and hold circuit in the first level.

13. The apparatus of claim 12, wherein:

the at least one additional level comprises a second level having two sample and hold circuits, wherein only one of the two sample and hold circuits samples the input voltage to produce the output voltage; and

a second bit in the digital output value is based on the output of the comparator associated with the sample and hold circuit in the second level that samples the input voltage.

14. The apparatus of claim 13, wherein:

the at least one additional level further comprises a third level having four sample and hold circuits, wherein only one of the four sample and hold circuits samples the input voltage to produce the output voltage; and

a third bit in the digital output value is based on the output of the comparator associated with the sample and hold circuit in the third level that samples the input voltage.

15. The apparatus of claim 14, wherein:

the analog-to-digital converter further comprises clock gating logic operable to receive an input clock signal and generate at least one additional clock signal; and

based on the input clock signal and the at least one additional clock signal, only one sample and hold circuit in each level of the sample and hold tree samples the input voltage for each cycle of the input clock signal.

16. The apparatus of claim 11, wherein the analog-to-digital converter further comprises a reference voltage ladder operable to produce the plurality of reference voltages.

17. The apparatus of claim 11, wherein:

the state machine produces an n-bit digital output value;

the plurality of comparators comprise 2_n−

1 comparators; and

the state machine is operable to resolve one bit of the digital output value for each cycle of an input clock signal.

18. A method, comprising:

sampling an input voltage to produce a first output voltage using a first sample and hold circuit;

comparing the first output voltage to a first threshold to identify a first bit of a digital value;

sampling the input voltage to produce a second output voltage using one of a plurality of second sample and hold circuits, the second sample and hold circuit selected based on the first bit; and

comparing the second output voltage to a second threshold to identify a second bit of the digital value.

19. The method of claim 18, further comprising:

sampling the input voltage to produce a third output voltage using one of a plurality of third sample and hold circuits, the third sample and hold circuit selected based on the second bit; and

comparing the third output voltage to a third threshold to identify a third bit of the digital value.

20. The method of claim 18, wherein:

the plurality of second sample and hold circuits comprise two sample and hold circuits; and

the plurality of the third sample and hold circuits comprise four sample and hold circuits.