Display device and method of manufacturing the same

• US 6,919,933 B2
• Filed: 03/22/2002
• Issued: 07/19/2005
• Est. Priority Date: 03/30/2001
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Fujitsu Display Technologies Corporation (Fujitsu Limited)
• Inventors: Uchida, Noriko, Zhang, Hongyong
• Primary Examiner(s): Kim, Robert H.
• Assistant Examiner(s): Akkapeddi, Prasad R.
• Application Number:
  US10/104,357
• Publication Number:
  US 20020139982A1
• Time in Patent Office: 1,215 Days
• Field of Search: 349/43, 257/71, 257/72, 257/59
• US Class Current: 349/43
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer

Abstract

In a semiconductor circuit in a display device, there are provided a first gate electrode of a first MOS transistor formed on a semiconductor layer via a gate insulating film, a second gate electrode of a second MOS transistor formed on the semiconductor layer via the gate insulating film at a distance from the first gate electrode, first and second one conductivity type impurity introduced regions formed in the semiconductor layer on both sides of the first gate electrode to serve as source/drain of the first MOS transistor, and first and second opposite conductivity type impurity introduced regions formed in the semiconductor layer on both sides of the second gate electrode to serve as source/drain of the second MOS transistor. One of the first and second opposite conductivity type impurity introduced regions is formed to contact mutually to the second one conductivity type impurity introduced region.

Claims

1. A display device comprising:

a semiconductor layer formed on an insulating substrate like an island;

a first gate electrode of a first MOS transistor formed on the semiconductor layer via a gate insulating film;

a second gate electrode of a second MOS transistor formed on the semiconductor layer via the gate insulating film at a distance from the first gate electrode;

first and second one conductivity type impurity introduced regions formed in the semiconductor layer on both sides of the first gate electrode to serve as source/drain of the first MOS transistor; and

first and second opposite conductivity type impurity introduced regions formed in the semiconductor layer on both sides of the second gate electrode to serve as source/drain of the second MOS transistor, whereby one of the first and second opposite conductivity type impurity introduced regions is formed to mutually contact the second one conductivity type impurity introduced region,

wherein the second one conductivity type impurity introduced region and the first opposite conductivity type impurity introduced region that contacts the second one conductivity type impurity introduced region are formed to engage alternatively along extending directions of the first and second gate electrodes, and a boundary portion between the second one conductivity type impurity introduced region and the first opposite conductivity type impurity introduced region is extended like the teeth of a comb.

2. A display device according to claim 1, wherein an impurity concentration of at least one of the first and second one conductivity type impurity introduced regions and the first and second opposite conductivity type impurity introduced regions is in excess of 1×

10¹⁹/cm³.

3. A display device according to claim 1, further comprising:

an insulating film for covering the first MOS transistor and the second MOS transistor;

a first hole formed in the insulating film on the second one conductivity type impurity introduced region;

a second hole formed in the insulating film on the first opposite conductivity type impurity introduced region that comes into contact with the second one conductivity type impurity introduced region; and

a wiring formed on the insulating film such that the wiring is ohmic-connected to the second one conductivity type impurity introduced region via the first hole and is ohmic-connected to the first opposite conductivity type impurity introduced region via the second hole.

4. A display device according to claim 3, wherein the wiring is formed of metal.

5. A display device according to claim 1, further comprising:

an insulating film for covering the first MOS transistor and the second MOS transistor;

a hole formed on a boundary between the second one conductivity type impurity introduced region and the first opposite conductivity type impurity introduced region that contacts to the second one conductivity type impurity introduced region; and

a wiring formed on the insulating film such that the wiring is ohmic-connected to the second one conductivity type impurity introduced region and the first opposite conductivity type impurity introduced region via the hole.

6. A display device according to claim 5, wherein the hole is formed in plural or the hole is formed like a slit.

7. A display device according to claim 5, wherein the wiring is formed of metal.

8. A display device according to claim 5, wherein the hole formed like the slit is formed at positions at which the second one conductivity type impurity introduced region and the first opposite conductivity type impurity introduced region are connected alternatively along its extending direction.

9. A display device according to claim 1, wherein the first MOS transistor and the second MOS transistor constitute a peripheral driving circuit or a signal processing circuit formed in a periphery of a display portion on the insulating substrate.

10. A display device according to claim 1, wherein the semiconductor layer is formed of a low-temperature polysilicon layer.

11. A display device manufacturing method comprising the steps of:

forming an amorphous semiconductor layer on an insulating substrate;

changing the amorphous semiconductor layer into a crystalline semiconductor layer by irradiating a laser beam onto the amorphous semiconductor layer or by annealing the amorphous semiconductor layer;

patterning the crystalline semiconductor layer into an island-like shape;

forming a first gate electrode of a first MOS transistor and a second gate electrode of a second MOS transistor on a first region and a second region of the island-like crystalline semiconductor layer via a gate insulating film respectively;

forming first and second one conductivity type impurity introduced regions serving as source/drain of the first MOS transistor by introducing one conductivity type impurity into the first region of the crystalline semiconductor layer on both sides of the first gate electrode;

forming first and second opposite conductivity type impurity introduced regions serving as source/drain of the second MOS transistor by introducing opposite conductivity type impurity into the second region of the crystalline semiconductor layer on both sides of the second gate electrode, whereby the first opposite conductivity type impurity introduced region is formed adjacently to the second one conductivity type impurity introduced region; and

forming an insulating film on the first MOS transistor and the second MOS transistor;

forming a first hole separately in the insulating film in the second one conductivity type impurity introduced region and the first opposite conductivity type impurity introduced region, or forming a second hole in the insulating film to extend over both the second one conductivity type impurity introduced region and the first opposite conductivity type impurity introduced region; and

forming a wiring, which is connected to the second one conductivity type impurity introduced region and the first opposite conductivity type impurity introduced region via the first hole or the second hole, on the insulating film,

wherein a planar shape of a boundary portion between the second one conductivity type impurity introduced region and the first opposite conductivity type impurity introduced region that contacts the second one conductivity type impurity introduced region is extended like the teeth of a comb along extending directions of the first gate electrode and the second gate electrode.

12. A display device manufacturing method according to claim 11, wherein an impurity concentration of at least ones of the first and second one conductivity type impurity introduced regions and the first and second opposite conductivity type impurity introduced regions is in excess of 1×

10¹⁹-cm³.

13. A display device manufacturing method according to claim 11, wherein the wiring is formed by forming a metal film on the insulating film and the first and second holes and then patterning the metal film.

14. A display device manufacturing method according to claim 11, wherein the first hole is formed at plural locations on the second one conductivity type impurity introduced region and is formed at plural locations on the first opposite conductivity type impurity introduced region.

15. A display device manufacturing method according to claim 11, wherein the second hole is formed like a slit, which is connected alternatively to the second one conductivity type impurity introduced region and the first opposite conductivity type impurity introduced region, along extending directions of the first gate electrode and the second gate electrode.