Semiconductor device and semiconductor memory device

• US 6,920,079 B2
• Filed: 07/30/2004
• Issued: 07/19/2005
• Est. Priority Date: 08/08/2003
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Shibayama, Akinori
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US10/902,133
• Publication Number:
  US 20050041499A1
• Time in Patent Office: 354 Days
• Field of Search: 365/230.06, 365/210, 365/63, 365/51
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

A semiconductor memory device according to the present invention includes: a plurality of N-ch MOS transistors arranged in an area surrounding a plurality of memory cells arranged in an array, at a spacing depending on a spacing of the plurality of memory cells, for driving the plurality of memory cells; and a plurality of dummy transistors 32-j each of which is formed between two adjacent ones of the plurality of N-ch MOS transistors 30-k so as to share diffusion layers with adjacent N-ch MOS transistors 30 and each of which has a gate electrode supplied with a voltage for electrically insulating these adjacent transistors 30-k.

Claims

1. A semiconductor device in which a plurality of elements identical in structure are arranged in an array, the semiconductor device comprising:

a plurality of transistors arranged in an area surrounding the plurality of elements arranged in the array, at a spacing depending on a spacing of the plurality of elements, for driving the plurality of elements; and

a plurality of dummy transistors each of which is formed between two adjacent ones of the plurality of transistors so as to share diffusion layers with the adjacent transistors and each of which has a gate electrode supplied with a voltage for electrically insulating the adjacent transistors.

2. A semiconductor memory device in which a plurality of memory cells are arranged in an array, the semiconductor device comprising:

a plurality of transistors arranged in an area surrounding the plurality of memory cells arranged in the array, at a spacing depending on a spacing of the plurality of memory cells, for driving the plurality of memory cells; and

a plurality of dummy transistors each of which is formed between two adjacent ones of the plurality of transistors so as to share diffusion layers with the adjacent transistors and each of which has a gate electrode supplied with a voltage for electrically insulating the adjacent transistors.

3. The semiconductor memory device according to claim 2, wherein

the plurality of transistors are N-ch MOS transistors.

4. The semiconductor memory device according to claim 3, wherein

a plurality of P-ch MOS transistors are arranged in parallel to the plurality of N-ch MOS transistors in the area surrounding the plurality of memory cells arranged in the array.

5. The semiconductor memory device according to claim 4, wherein

an N-ch MOS transistor located at an end of an arrangement of the plurality of N-ch transistors has a diffusion layer that is longer than a diffusion layer of a P-ch MOS transistor located at an end of an arrangement of the plurality of P-ch transistors.

6. The semiconductor memory device according to claim 5, wherein

at least one of the dummy transistors is formed outside of the N-ch MOS transistor located at the end.

7. The semiconductor memory device according to claim 3, wherein

the plurality of memory cells are arranged in the array in a first rectangular area,

the semiconductor memory device further comprises a plurality of unoperable dummy memory cells arranged so as to surround sides of the first rectangular area,

the plurality of N-ch MOS transistors are arranged in a second rectangular area adjacent to a dummy-memory-cell area in which the plurality of dummy memory cells are arranged and having one side corresponding to one side of the first rectangular area, and

an N-ch MOS transistor located at an end of an arrangement of the N-ch MOS transistors in the second rectangular area has an active region extending to a third area that is in contact with the second rectangular area that includes the plurality of N-ch MOS transistors and in contact with a part of one side of the dummy-memory-cell area.

8. The semiconductor memory device according to claim 7, wherein

at least one of the dummy transistors is formed on the active region extending to the third area.

9. The semiconductor memory device according to claim 4, wherein

the plurality of N-ch MOS transistors and the plurality of P-ch MOS transistors are respectively isolated through Shallow Trench Isolation (STI).

10. The semiconductor memory device according to claim 4, wherein

the plurality of N-ch MOS transistors and the plurality of P-ch MOS transistors are used for word drivers for driving a plurality of word lines for selecting a row of the memory cells arranged in the array.

11. The semiconductor memory device according to claim 10, wherein

one of the plurality of N-ch MOS transistors and one of the plurality of P-ch MOS transistors form a CMOS inverter, and

an output of the CMOS inverter is coupled to a word line and a diffusion layer of one of the dummy transistors.

12. The semiconductor memory device according to claim 4, wherein

the plurality of N-ch MOS transistors and the plurality of P-ch MOS transistors are used for a plurality of switches for driving a plurality of bit lines for reading a signal from the plurality of memory cells.

13. The semiconductor memory device according to claim 12, wherein

each of the switches is configured by connecting a diffusion layer of one of the N-ch MOS transistors and a diffusion layer of one of the P-ch MOS transistors together and connecting a gate of the one of the N-ch MOS transistors and a gate of the one of the P-ch MOS transistors through a signal line.

14. The semiconductor memory device according to claim 4, wherein

the plurality of N-ch MOS transistors and the plurality of P-ch MOS transistors are used for a plurality of sense amplifiers that amplify the signal read from the plurality of memory cells.

15. The semiconductor memory device according to claim 14, wherein

each of the dummy transistors is placed so as to connect diffusion layers of N-ch MOS transistors included in adjacent sense amplifiers.

16. The semiconductor memory device according to claim 15, wherein

a diffusion layer of each of the dummy transistor is connected to a signal line to which the signal amplified by the sense amplifier is output.