Adaptive radio transceiver with floating MOSFET capacitors

• US 6,920,311 B2
• Filed: 03/09/2004
• Issued: 07/19/2005
• Est. Priority Date: 10/21/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Maryam, Khorram, Shahla, Rofougaran, Ahmadreza
• Primary Examiner(s): Milord, Marceau
• Application Number:
  US10/796,817
• Publication Number:
  US 20040195917A1
• Time in Patent Office: 497 Days
• Field of Search: 455/66.1, 455/76, 455/86, 455/73, 455/77, 455/83, 455/323, 455/313, 455/78, 455/75, 327/427, 327/434, 361/281, 361/270, 361/301.1, 361/277
• US Class Current: 455/66.1
• CPC Class Codes: H03B 21/01 by beating unmodulated signals of different frequencies
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 2203/45386 the AAC comprising one or more coils in the source circuit
• CPC Class Codes: H03F 2203/45526 the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45528 the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03G 11/00 Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
• CPC Class Codes: H03G 3/001 Digital control of analog signals
• CPC Class Codes: H03H 11/126 using a single operational amplifier H03H11/1204 takes precedence; parallel-T filters H03H11/1295
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03H 11/22 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03H 11/344 : Duplexers
• CPC Class Codes: H03H 2011/0494 : Complex filters
• CPC Class Codes: H03H 21/0001 : Analogue adaptive filters
• CPC Class Codes: H03H 21/0012 : Digital adaptive filters
• CPC Class Codes: H03H 2210/025 : Capacitor
• CPC Class Codes: H03H 2210/036 : Stepwise
• CPC Class Codes: H03H 7/42 : Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 7/099 : concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/18 : using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H04B 17/104 : of other parameters, e.g. DC offset, delay or propagation times
• CPC Class Codes: H04B 17/14 : of the whole transmission and reception path, e.g. self-test loop-back
• CPC Class Codes: H04B 17/19 : Self-testing arrangements

Abstract

An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Claims

1. A capacitor, comprising:

a first node that receives a signal;

a first transistor comprising a gate node and at least one other node, the at least one other node being coupled to receive the signal from the first node; and

a second transistor comprising a gate node and at least one other node, the gate node of the second transistor being coupled to receive the signal from the gate node of the first transistor.

2. The capacitor according to claim 1, wherein at least one of the first transistor and the second transistor comprises a metal-oxide-semiconductor (MOS) transistor.

3. The capacitor according to claim 1, wherein the capacitor is a floating capacitor.

4. The capacitor according to claim 1, further comprising:

a resistor coupled to the gate node of the first transistor and to the gate node of the second transistor.

5. The capacitor according to claim 1, wherein the at least one other node of the first transistor comprises a first transistor node and a second transistor node, the first transistor node being coupled to the second transistor node and to the first node.

6. The capacitor according to claim 1, further comprising:

a second node coupled to receive the signal from the at least one other node of the second transistor.

7. The capacitor according to claim 6, wherein the first transistor and the second transistor provide a capacitance between the first node and the second node.

8. The capacitor according to claim 6, wherein the at least one other node of the second transistor comprises a first transistor node and a second transistor node, the first transistor node being coupled to the second transistor node and to the second node.

9. The capacitor according to claim 1, further comprising:

a bias source coupled to the gate node of the first transistor and to the gate node of the second transistor.

10. A capacitor, comprising:

a first transistor comprising a first node, a second node and a third node, the first node being coupled to the second node; and

a second transistor comprising a fourth node, a fifth node and a sixth node, the fourth node being coupled to the fifth node, the sixth node being coupled to the third node,

wherein the first transistor and the second transistor provide a capacitance between the first node and the fourth node.

11. The capacitor according to claim 10, wherein at least one of the first transistor and the second transistor comprises a metal-insulator-semiconductor transistor.

12. The capacitor according to claim 10, wherein the capacitor is a floating capacitor.

13. The capacitor according to claim 10,

wherein the first node or the fourth node comprises a drain node,

wherein the second node or the fifth node comprises a source node, and

wherein the third node or the sixth node comprises a gate node.

14. The capacitor according to claim 10, further comprising:

a bias source coupled to the third node and to the sixth node via a bias resistor.

15. The capacitor according to claim 10, further comprising:

a first signal node coupled to the first node and to the second node; and

a second signal node coupled to the fourth node and to the fifth node.

16. The capacitor according to claim 15, wherein the first signal node and the second signal node provide the capacitance.

17. The capacitor according to claim 15, wherein the signal passes from the first signal node to the second signal node via the first transistor and the second transistor.

18. A method for providing a capacitance, comprising:

receiving a signal at a non-gate node of a first transistor;

sending the signal, received by the first transistor, from a gate node of the first transistor to a gate node of a second transistor; and

sending the signal, received by the second transistor, to a non-gate node of the second transistor.

19. The method according to claim 18, wherein at least one of the first transistor and the second transistor comprises a metal-insulator-semiconductor transistor.

20. The method according to claim 19, wherein the metal-insulator-semiconductor transistor comprises a MOS transistor.

21. The method according to claim 18, wherein the capacitance is a floating capacitance.

22. The method according to claim 18, wherein the first transistor comprises a second non-gate node, the second non-gate node being coupled to the non-gate node of the first transistor.

23. An integrated circuit, comprising:

a first node that receives a signal;

a first transistor comprising a gate node and at least one other node, the at least one other node being coupled to receive the signal from the first node; and

a second transistor comprising a gate node and at least one other node, the gate node of the second transistor being coupled to receive the signal from the gate node of the first transistor.

24. The integrated circuit according to claim 23, wherein at least one of the first transistor and the second transistor comprises a metal-oxide-semiconductor (MOS) transistor.

25. The integrated circuit according to claim 23, wherein the capacitor is a floating capacitor.

26. The integrated circuit according to claim 23, wherein the at least one other node of the first transistor comprises a first transistor node and a second transistor node, the first transistor node being coupled to the second transistor node and to the first node.

27. The integrated circuit according to claim 23, further comprising:

a second node coupled to receive the signal from the at least one other node of the second transistor.

28. The integrated circuit according to claim 27, wherein the first transistor and the second transistor provide a capacitance between the first node and the second node.

29. The integrated circuit according to claim 23, wherein the at least one other node of the second transistor comprises a first transistor node and a second transistor node, the first transistor node being coupled to the second transistor node and to the second node.

30. The integrated circuit according to claim 23, further comprising:

a bias source coupled to the gate node of the first transistor and to the gate node of the second transistor.

31. An integrated circuit, comprising:

a first transistor comprising a first node, a second node and a third node, the first node being coupled to the second node; and

a second transistor comprising a fourth node, a fifth node and a sixth node, the fourth node being coupled to the fifth node, the sixth node being coupled to the third node,

wherein the first transistor and the second transistor provide a capacitance between the first node and the fourth node.

32. The integrated circuit according to claim 31, wherein at least one of the first transistor and the second transistor comprises a metal-insulator-semiconductor transistor.

33. The integrated circuit according to claim 31, wherein the capacitor is a floating capacitor.

34. The integrated circuit according to claim 31,

wherein the first node or the fourth node comprises a drain node,

wherein the second node or the fifth node comprises a source node and

wherein the third node or the sixth node comprises a gate node.

35. The integrated circuit according to claim 31, further comprising:

a bias source coupled to the third node via a bias resistor and to the sixth node via the bias resistor.

36. The integrated circuit according to claim 31, further comprising:

a first signal node coupled to the first node and to the second node; and

a second signal node coupled to the fourth node and to the fifth node.

37. The integrated circuit according to claim 36, wherein the capacitance is formed between the first signal node and the second signal node.

38. A tunable capacitor array, comprising:

a plurality of capacitors, each capacitor comprising;

a first node that receives a signal,

a first transistor comprising a gate node and at least one other node, the at least one other node being coupled to receive the signal from the first node, and

a second transistor comprising a gate node and at least one other node, the gate node of the second transistor being coupled to receive the signal from the gate node of the first transistor; and

a plurality of switches, each switch being coupled to a corresponding capacitor of the plurality of capacitors.

39. The tunable capacitor array according to claim 38, wherein at least one of the first transistor and the second transistor comprises a metal-oxide-semiconductor (MOS) transistor.

40. The tunable capacitor array according to claim 38, wherein the capacitor is a floating capacitor.

41. The tunable capacitor array according to claim 38, wherein the at least one other node of the first transistor comprises a first transistor node and a second transistor node, the first transistor node being coupled to the second transistor node and to the first node.

42. The tunable capacitor array according to claim 38, further comprising:

a second node coupled to receive the signal from the at least one other node of the second transistor.

43. The capacitor according to claim 42, wherein the first transistor and the second transistor provide a capacitance between the first node and the second node.

44. The tunable capacitor array according to claim 42, wherein the at least one other node of the second transistor comprises a first transistor node and a second transistor node, the first transistor node being coupled to the second transistor node and to the second node.

45. The tunable capacitor array according to claim 38, further comprising:

a bias source coupled to the gate node of the first transistor and to the gate node of the second transistor.

46. A tunable capacitor array, comprising:

a plurality of capacitors, each capacitor comprising;

a first transistor comprising a first node, a second node and a third node, the first node being coupled to the second node, and

a second transistor comprising a fourth node, a fifth node and a sixth node, the fourth node being coupled to the fifth node, the sixth node being coupled to the third node,

wherein the first transistor and the second transistor form a capacitance between the first node and the fourth node; and

a plurality of switches, each switch being coupled to a corresponding capacitor of the plurality of capacitors.

47. The tunable capacitor array according to claim 46, wherein at least one of the first transistor and the second transistor comprises a metal-insulator-semiconductor transistor.

48. The tunable capacitor array according to claim 46, wherein the capacitor is a floating capacitor.

49. The tunable capacitor array according to claim 46,

wherein the first node or the fourth node comprises a drain node,

wherein the second node or the fifth node comprises a source node, and

wherein the third node or the sixth node comprises a gate node.

50. The tunable capacitor array according to claim 46, further comprising:

a bias source coupled to the third node via a bias resistor and to the sixth node via the bias resistor.

51. The tunable capacitor array according to claim 46, further comprising:

a first signal node coupled to the first node and to the second node; and

a second signal node coupled to the fourth node and to the fifth node.

52. The tunable capacitor array according to claim 51, wherein the capacitance is formed between the first signal node and the second signal node.