Test structures and methods for inspection of semiconductor integrated circuits

• US 6,921,672 B2
• Filed: 01/07/2003
• Issued: 07/26/2005
• Est. Priority Date: 12/14/1999
• Status: Expired due to Term

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Walker, David J., Weiner, Kurt H., Pinto, Gustavo A., Mantalas, Lynda C., Long, Robert Thomas, Satya, Akella V. S., Adler, David L., Richardson, Neil
• Primary Examiner(s): Thompson, Craig A.
• Assistant Examiner(s): Pham, Thanhha
• Application Number:
  US10/338,936
• Publication Number:
  US 20030096436A1
• Time in Patent Office: 931 Days
• Field of Search: 438/14, 438 16- 18, 324/393, 324/395, 324/397, 324/399, 324500-501, 324508-509, 324/512, 324/522, 324527-528, 324/537, 324/765, 324750-751
• US Class Current: 438/18
• CPC Class Codes: G01N 21/66 electrically excited, e.g. electroluminescence
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: H01J 2237/2817 Pattern inspection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Claims

1. A method for forming a semiconductor die, the method comprising:

providing a plurality of electrically non-isolated test structures that each have a first portion and a second portion and are alternating with a plurality of electrically isolated test structures that each have a first portion and a second portion, wherein a width of each first portion of the electrically non-isolated test structures is equal to or less than a width of each second portion of the electrically non-isolated test structures;

scanning a charged particle beam over the first portions of the electrically non-isolated test structures and the first portions of the electrically isolated test structures to thereby perform a voltage contrast inspection on the electrically non-isolated test structures and the electrically isolated test structures without scanning the second portions of the electrically non-isolated test structures and the second portions of the electrically isolated test structures;

determining whether there is an open type defect within the second portions of the electrically non-isolated test structures based on the voltage contrast inspection of the first portions of the electrically non-isolated test structures.

2. A method as recited in claim 1, wherein the electrically isolated test structures are formed from a same conductive layer as the electrically non-isolated test structures.

3. A method as recited in claim 1, wherein the electrically isolated test structures are formed from a different conductive layer as the electrically non-isolated test structures.

4. A method as recited in claim 1, wherein the electrically non-isolated test structures are coupled with a substrate of the semiconductor die.

5. A method as recited in claim 1, wherein the second portion of the electrically isolated test structure is substantially larger than the first portion of electrically isolated test structure.

6. A method as recited in claim 1, wherein the second portion of the non-electrically isolated test structure is substantially larger than the first portion of non-electrically isolated test structure.

7. A method for forming a semiconductor die, the method comprising:

providing a plurality of electrically non-isolated test structures that each have a first portion and a second portion and are alternating with a plurality of electrically isolated test structures that each have a first portion and a second portion, wherein a width of each first portion of the electrically non-isolated test structures is equal to or less than a width of each second portion of the electrically non-isolated test structures;

scanning a charged particle beam over the first portions of the electrically non-isolated test structures and the first portions of the electrically isolated test structures to thereby perform a voltage contrast inspection on the electrically non-isolated test structures and the electrically isolated test structures without scanning the second portions of the electrically non-isolated test structures and the electrically isolated test structures;

determining whether there is an electrical defect within the second portions of the electrically non-isolated test structures based on the voltage contrast inspection of the first portions of the electrically non-isolated test structures.

8. A method as recited in claim 7, wherein the electrically isolated test structures are formed from a same conductive layer as the electrically non-isolated test structures.

9. A method as recited in claim 7, wherein the electrically isolated test structures are formed from a different conductive layer as the electrically non-isolated test structures.

10. A method as recited in claim 7, wherein the electrically non-isolated test structures are coupled with a substrate of the semiconductor die.

11. A method as recited in claim 7, wherein the second portion of the electrically isolated test structure is substantially larger than the first portion of electrically isolated test structure.

12. A method as recited in claim 7, wherein the second portion of the non-electrically isolated test structure is substantially larger than the first portion of non-electrically isolated test structure.