Method for forming metal replacement gate of high performance

• US 6,921,711 B2
• Filed: 09/09/2003
• Issued: 07/26/2005
• Est. Priority Date: 09/09/2003
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Wang, Yun-Yu, Narayanan, Vijay, Li, Ying, Cabral, Cyril Jr., Jamison, Paul C., Ku, Victor, Steegen, An L, Wong, Kwong H.
• Primary Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/605,106
• Publication Number:
  US 20050051854A1
• Time in Patent Office: 686 Days
• Field of Search: 438/259, 438/270, 438/589, 438/592, 438/595, 438/926, 257/412, 257/751, 257/753
• US Class Current: 438/589
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

Claims

1. A method of fabricating a gate structure of an integrated circuit, comprising:

forming a metal-containing gate in an opening within a dielectric region formerly occupied by a sacrificial gate, said metal-containing gate including;

a first layer deposited via a chemical vapor deposition (CVD) process using a carbonyl of a metal as a deposition precursor, the first layer contacting a gate dielectric, the gate dielectric contacting a transistor channel region in a semiconductor region of a substrate;

a diffusion barrier layer overlying said first layer; and

a second layer overlying said diffusion barrier layer,

wherein said first layer is thinner than said second layer and said first layer is between 2 nm and 10 nm thick.

2. The method of claim 1 wherein said diffusion barrier layer is annealed before forming the second layer.

3. The method of claim 2 further comprising the step of annealing said diffusion barrier at a temperature ranging between 400 and 600 degrees Celsius.

4. The method of claim 3, wherein said second layer is deposited using a chemical vapor deposition (CVD) process.

5. The method of claim 4 wherein said second layer is deposited using a fluorine containing compound gas of a metal as a deposition precursor.

6. The method of claim 1 wherein second layer of metal is deposited from a fluorine containing precursor.

7. The method of claim 1 wherein said first layer consists essentially of at least one material selected from the group consisting of iridium (Ir), niobium (Nb), platinum (Pt), rhenium (Re), rhodium (Rh), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten (W), and vanadium (V).

8. The method of claim 1 wherein said second layer consists essentially of at least one material selected from the group consisting of iridium (Ir), niobium (Nb), platinum (Pt), rhenium (Re), rhodium (Rh), ruthenium (Ru), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten (W), vanadium (V), nickel (Ni) silicide, cobalt (Co) silicide and titanium (Ti) silicide.

9. The method of claim 1 wherein at least one of said first layer and said second layer includes an impurity concentration to adjust said metal gate to a desired workfunction.

10. The method of claim 1 further comprising depositing a layer of adhesion material prior to forming said diffusion barrier layer.

11. The method of claim 10 wherein said diffusion barrier layer consists essentially of titanium nitride (TiN) and said adhesion material consists essentially of titanium (Ti).

12. The method of claim 1 wherein said diffusion barrier layer includes at least one of a nitride of titanium, a nitride of hafnium and a nitride of zirconium.

13. The method of claim 12, wherein said diffusion barrier layer is formed by depositing TiN after depositing titanium.

14. The method of claim 12 wherein said diffusion barrier layer consists essentially of TiN.

15. The method of claim 1 wherein said dielectric region includes a pair of spacers disposed at sidewalls of said opening.

16. The method of claim 15 wherein said dielectric region includes an interlevel dielectric layer extending from sides of said spacers over said semiconductor region and said metal gate is planarized to a level of said interlevel dielectric layer.

17. The method of claim 16 wherein said metal gate is planarized by chemical mechanical polishing.

18. The method of claim 1 wherein said substrate is selected from the group consisting of a bulk semiconductor substrate, semiconductor-on-insulator substrate, silicon-on-insulator substrate, silicon germanium substrate and germanium substrate.

19. The method of claim 1 wherein said semiconductor region includes a thin film of semiconductor having a polycrystalline or amorphous form.

20. The method of claim 1 wherein said sacrificial gate is removed from the opening by etching and said method further comprises removing an etch stop layer disposed between the sacrificial gate and the semiconductor region and thereafter forming the gate dielectric.

21. The method of claim 20 wherein the gate dielectric has a different thickness than the etch stop layer.

22. The method of claim 21, wherein said etch stop layer consists essentially of a layer of oxide.

23. The method of claim 1, wherein said sacrificial gate consists essentially of polysilicon.

24. A method of fabricating a gate structure of an integrated circuit, comprising:

forming a metal-containing gate in an opening within a dielectric region formerly occupied by a sacrificial gate, said metal-containing gate including;

a first layer consisting essentially of tungsten deposited from a W(CO)₆ precursor, said first layer contacting a gate dielectric, the gate dielectric contacting a transistor channel region formed in a semiconductor region of a substrate;

a diffusion barrier layer overlying said first layer; and

a second layer overlying said diffusion barrier layer, said second layer consisting essentially of tungsten deposited from a WF₆ precursor, at least one of said first layer and said second layer including an impurity concentration to adjust said metal gate to a desired workfunction.

25. A method of making a metal gate structure on a substrate comprising:

forming an etch stop layer on a semiconductor region of a substrate;

forming a sacrificial gate on said etch stop layer;

providing a pair of dielectric spacers on sidewalls of said sacrificial gate;

forming a dielectric layer on said substrate having a top surface generally planar to a top of said sacrificial gate;

removing said sacrificial gate to form an opening between said spacers;

removing said etch stop layer from under said opening;

forming a gate dielectric on said semiconductor region under said opening;

depositing from a W(CO)₆ a first layer consisting essentially of tungsten in said opening, said first layer contacting said gate dielectric and sidewalls of said spacers;

forming a diffusion barrier layer on said first layer in said opening; and

depositing a from a W(CO)₆ a second layer consisting essentially of tungsten in said opening, said second layer contacting said diffusion barrier layer.