Power MOSFET and method for forming same using a self-aligned body implant

• US 6,921,939 B2
• Filed: 04/27/2001
• Issued: 07/26/2005
• Est. Priority Date: 07/20/2000
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Zeng, Jun
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Soward, Ida M.
• Application Number:
  US09/844,347
• Publication Number:
  US 20020008284A1
• Time in Patent Office: 1,551 Days
• Field of Search: 257301-305, 257/905, 257328-334
• US Class Current: 257/330
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench

Abstract

A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the trench, and forming a dielectric layer to fill an upper portion of the trench. Portions of the semiconductor layer laterally adjacent the dielectric layer are removed so that an upper portion thereof extends outwardly from the semiconductor layer. Spacers are formed laterally adjacent the outwardly extending upper portion of the dielectric layer, the spacers are used as a self-aligned mask for defining source/body contact regions.

Claims

1. A MOSFET comprising:

a semiconductor layer having a trench therein;

a gate conducting layer in a lower portion of said trench;

a dielectric layer in an upper portion of said trench;

source regions adjacent said dielectric layer; and

source/body contact regions laterally spaced apart from said trench and being recessed within said semiconductor layer and non-interruptively contacting said source regions;

said dielectric layer extending outwardly from said semiconductor layer, said source regions and said source/body contact regions, and said outwardly extending dielectric layer having sidewalls aligned with sidewalls of said trench.

2. A MOSFET according to claim 1, further comprising a source electrode on said source regions and on said dielectric layer.

3. A MOSFET according to claim 2, further comprising at least one conductive via between said source electrode and said source/body contact regions.

4. A MOSFET according to claim 1, wherein a portion of said source regions include a recess over said source/body contact regions.

5. A MOSFET according to claim 1, wherein a portion of said source regions include an opening exposing said source/body contact regions;

and further comprising a source electrode on said source regions, on said dielectric layer, and on said source/body contact regions.

6. A MOSFET according to claim 1, wherein said outwardly extending dielectric layer extends from said source regions equal to or less than about 1 micron.

7. A MOSFET according to claim 1, wherein said gate is recessed in said trench within a range of about 0.2 to 0.8 microns from an opening thereof.

8. A MOSFET according to claim 1, wherein an upper surface of the recess is equal to or less than a depth of about 1 micron from a surface of the semiconductor layer.

9. A MOSFET comprising:

a semiconductor layer having a trench therein;

a gate dielectric layer lining said trench;

a gate conducting layer in a lower portion of said trench;

a dielectric layer in an upper portion of said trench;

source regions adjacent said dielectric layer;

source/body contact regions laterally spaced from said gate conducting layer and non-interruptively contacting said source regions;

said dielectric layer extending outwardly from said semiconductor layer, said source regions and said source/body contact regions, and said outwardly extending dielectric layer having sidewalls aligned with sidewalls of said trench;

a source electrode on said source regions and on said dielectric layer; and

at least one conductive via between said source electrode and said source/body contact regions and extending through said source regions.

10. A MOSFET according to claim 9, wherein a portion of said source regions include a recess over said source/body contact regions.

11. A MOSFET according to claim 9, wherein said outwardly extending dielectric layer extends from said source regions equal to or less than about 1 micron.

12. A MOSFET according to claim 9, wherein said gate conducting layer is recessed in said trench within a range of about 0.2 to 0.8 microns from an opening thereof.

13. A MOSFET comprising:

a semiconductor layer having a trench therein;

a gate dielectric layer lining said trench;

a gate conducting layer in a lower portion of said trench;

a dielectric layer in an upper portion of said trench and extending outwardly from said semiconductor layer;

source regions adjacent said dielectric layer and including an opening therein; and

source/body contact regions laterally spaced from said gate conducting layer and non-interruptively contacting said source regions, said source/body contact regions being exposed by the opening in said source regions;

said dielectric layer extending outwardly from said semiconductor layer, said source regions and said source/body contact regions, and said outwardly extending dielectric layer having sidewalls aligned with sidewalls of said trench.

14. A MOSFET according to claim 13, further comprising a source electrode on said source regions, on said dielectric layer, and on said source/body contact regions.

15. A MOSFET according to claim 13, wherein said outwardly extending dielectric layer extends from said source regions equal to or less than about 1 micron.

16. A MOSFET according to claim 13, wherein said gate conducting layer is recessed in said trench within a range of about 0.2 to 0.8 microns from an opening thereof.