Narrow fin FinFET

• US 6,921,963 B2
• Filed: 04/23/2004
• Issued: 07/26/2005
• Est. Priority Date: 01/23/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Krivokapic, Zoran, Dakshina-Murthy, Srikanteswara, Yu, Bin, Wang, Haihong, An, Judy Xilin
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HO, TU TU V
• Application Number:
  US10/830,006
• Publication Number:
  US 20040197975A1
• Time in Patent Office: 459 Days
• Field of Search: 257/618, 257/327, 257/347
• US Class Current: 257/618
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.

Claims

1. A MOSFET device comprising:

a source and a drain formed on an insulating layer;

a fin structure formed on the insulating layer between the source and the drain, the fin structure including a first region formed in a channel area of the fin structure;

a dielectric layer formed around at least a channel portion of the fin structure to a thickness ranging from 0.6 nm to less than 1.0 nm;

a protective layer formed over at least the first region of the fin structure, the protective layer being wider than the first region and including an oxide layer and a nitride layer formed over the oxide layer and having a thickness ranging from 50 nm to 75 nm; and

a gate formed on the insulating layer around at least a portion of the fin structure.

2. The MOSFET device of claim 1, wherein the first region has a width of about 3 to 6 nm.

3. The MOSFET device of claim 1, wherein the gate comprises polysilicon.

4. The MOSFET device of claim 1, wherein the MOSFET device is a FinFET.

5. The MOSFET device of claim 1, wherein the gate is formed to include small gate lengths.

6. A method for forming a MOSFET device comprising:

forming a source, a drain, and a fin structure on an insulating layer, portions of the fin structure acting as a channel for the MOSFET;

forming a protective layer above the fin structure;

depositing a tetraethyorthosilicate (TEOS) layer over the MOSFET device before trimming the fin structure;

forming a polysilicon layer to a thickness ranging from about 50 nm to 70 nm on the TEOS layer;

trimming the fin structure without significantly trimming the protective layer; and

depositing a second polysilicon layer to act as a gate area for the MOSFET.

7. The method of claim 6, wherein the fin structure is trimmed by exposing the fin structure to NH₄OH.

8. The method of claim 6, wherein forming the protective layer includes:

depositing an oxide layer to a depth of about 15 nm, and

depositing a nitride layer to a depth of about 50 nm to 75 nm.

9. The method of claim 6, further comprising:

etching away the TEOS layer over the fin structure before trimming the fin structure.

10. The method of claim 6, wherein trimming the fin structure includes trimming the fin structure to a width of about 3 nm to 6 nm.