Stacked flip chip package

• US 6,921,968 B2
• Filed: 04/30/2004
• Issued: 07/26/2005
• Est. Priority Date: 05/02/2003
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chung, Chih-Ming
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US10/834,936
• Publication Number:
  US 20040217485A1
• Time in Patent Office: 452 Days
• Field of Search: 257685-686, 257/738, 257/777, 257/778, 257/782, 257/784, 257/787, 257/796
• US Class Current: 257/686
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/91 : Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A stacked flip-chip package comprises a substrate having an opening, a back-to-face chip module, and an encapsulant. The back-to-face chip module is attached to the substrate and encapsulated by the encapsulant. The back-to-face chip module includes a first chip and a second chip. The first chip has a first active surface and a first back surface. Redistributed traces are formed on the first back surface. The second chip is flip-chip mounted on the first back surface of the first chip and electrically connected to the redistributed traces. A plurality of bumps connect the redistributed traces to the top surface of the substrate. Thus the second chip can be accommodated inside the opening and the redistributed traces are electrically connected to the second chip and the substrate so as to achieve fine pitch flip-chip mounting and improve the electrical performance and heat dissipation efficiency for the back-to-face chip module.

Claims

1. A stacked flip-chip package comprising:

a substrate having a top surface, a bottom surface and an opening;

a back-to-face chip module including a first chip and a second chip, wherein the first chip has a first active surface, a first back surface, and a plurality of first bonding pads, the second chip has a second active surface, a second back surface, and a plurality of second bonding pads, a plurality of redistributed traces are formed on the first back surface of the first chip and have a plurality of first bumping pads and a plurality of second bumping pads, the first bumping pads are formed at the periphery of the first back surface of the first chip in fan-out arrangement, the second bumping pads are formed on the center of the first back surface of the first chip in fan-in arrangement, the second chip is flip-chip mounted on the first back surface of the first chip so that the second bonding pads are electrically connected to the second bumping pads, the back-to-face chi module is attached to the top surface of the substrate in a manner that the first bumping pads are electrically connected to the top surface of the substrate and the second chip is accommodated inside the opening; and

an encapsulant formed on the top surface of the substrate to encapsulate the back-to-face chip module.

2. The package in accordance with claim 1, wherein the second back surface is exposed out of the bottom surface of the substrate.

3. The package in accordance with claim 2, further comprising a heat sink attached to the second back surface of the second chip.

4. The package in accordance with claim 3, wherein the heat sink is connected to the bottom surface of the substrate to cover the opening.

5. The package in accordance with claim 1, further comprising a plurality of solder balls placed on the bottom surface of the substrate.

6. The package in accordance with claim 1, further comprising an under-filling material between the first back surface of the first chip and the second active surface of the second chip.

7. The package in accordance with claim 1, further comprising a plurality of bonding wires connecting the first bonding pads to the substrate.