Leadless chip carrier design and structure
First Claim
1. A structure comprising:
- a substrate having a top surface for receiving a chip, said chip having at least one device electrode;
a die attach bond pad attached to said top surface of said substrate;
a printed circuit board attached to a bottom surface of said substrate;
at least one signal via in said substrate;
at least one bond pad abutting said at least one signal via, said at least one bond pad providing electrical connection between said at least one device electrode of said chip and said printed circuit board;
a plurality of separate thermally conductive vias in said substrate, each of said plurality of separate thermally conductive vias being coupled to a heat spreader, said heat spreader being directly attached to said bottom surface of said substrate;
a downbond coupling said chip to said die attach bond pad.
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0 Petitions
Accused Products
Abstract
A semiconductor device is provided in the form of a chip carrier (e.g., chip/IC scale carrier for RF applications) that includes an integrated circuit chip attached to a die attach pad. The device has an interconnect substrate having an upper surface and a lower surface, with a plurality of vias passing through the thickness of the interconnect substrate from the upper surface to the lower surface. The die attach pad is located on the upper surface of the interconnect substrate, and a heat spreader is located on the lower surface of the interconnect substrate. A first group of vias is positioned to intersect both the die attach pad and the heat spreader. A second group of vias is positioned away from the die attach pad and the heat spreader. The upper surface has a plurality of bond pads that are abutting the second group of vias and the lower surface has a plurality of lands that are also abutting the second group of vias.
29 Citations
25 Claims
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1. A structure comprising:
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a substrate having a top surface for receiving a chip, said chip having at least one device electrode; a die attach bond pad attached to said top surface of said substrate; a printed circuit board attached to a bottom surface of said substrate; at least one signal via in said substrate; at least one bond pad abutting said at least one signal via, said at least one bond pad providing electrical connection between said at least one device electrode of said chip and said printed circuit board; a plurality of separate thermally conductive vias in said substrate, each of said plurality of separate thermally conductive vias being coupled to a heat spreader, said heat spreader being directly attached to said bottom surface of said substrate; a downbond coupling said chip to said die attach bond pad. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A structure comprising:
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a substrate having a top surface and a bottom surface; a die attach bond pad attached to said top surface of said substrate; a semiconductor chip attached to said top surface of said substrate, said semiconductor chip having a plurality of device electrodes; a heat spreader directly attached to said bottom surface of said substrate; a first plurality of separate thermally conductive vias in said substrate, said first plurality of separate thermally conductive vias providing a connection between said semiconductor chip and said heat spreader; a plurality of bond pads and a second plurality of signal vias arranged such that each one of said plurality of bond pads abuts a separate one of said second plurality of signal vias; a downbond coupling said chip to said die attach bond pad. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25)
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Specification