Circuit device with at least partial packaging, exposed active surface and a voltage reference plane

• US 6,921,975 B2
• Filed: 04/18/2003
• Issued: 07/26/2005
• Est. Priority Date: 04/18/2003
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Leal, George R., Wenzel, Robert J., Sawyer, Brian D., Wontor, David G., Prack, Edward R., Mangrum, Marc Alan, Zhao, Jie-Hua
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US10/418,790
• Publication Number:
  US 20040207077A1
• Time in Patent Office: 830 Days
• Field of Search: 257/686, 257/685, 257/723, 257/777, 257/684, 257/796, 257/787, 257/712, 257/713, 257/691, 257/698
• US Class Current: 257/723
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device (115) may be placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). The conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126,326) may be electrically conductive or electrically non-conductive.

Claims

1. A device with at least partial packaging, comprising:

a circuit device having a first surface and a second surface opposite the first surface, wherein the first surface comprises active circuitry;

an electrically conductive layer having a first surface, a second surface opposite the first surface, and at least one opening, wherein;

the at least one opening at least partially surrounds the circuit device,

the first surface of the circuit device is substantially coplanar with the first surface of the electrically conductive layer, and

the electrically conductive layer comprises a first reference voltage plane;

an electrical contact, electrically coupled to the first reference voltage plane, said electrical contact enabling electrical contact to be made to said first reference voltage plane; and

an encapsulant layer at least partially filling a gap within the at least one opening between the circuit device and the electrically conductive layer, wherein the electrically conductive layer comprises at least two portions which are electrically isolated from each other.

2. The device of claim 1, wherein one of the at least two portions comprises the first voltage reference plane.

3. The device of claim 2, wherein another one of the at least two portions comprises a second voltage reference plane.

4. The device of claim 3, further comprising a second circuit device having a first terminal coupled to the first voltage reference plane and a second terminal coupled to the second voltage reference plane.

5. The device of claim 1, further comprising an interconnect layer overlying the first surfaces of the circuit device and the electrically conductive layer.

6. The device of claim 5, wherein the interconnect layer comprises a plurality of interconnect levels.

7. The device of claim 5, further comprising a compliant layer overlying the interconnect layer.

8. The device of claim 7, wherein the compliant layer comprises a plurality of electrically conductive vias coupled to the interconnect layer.

9. The device of claim 8, further comprising a plurality of conductive balls coupled to the electrically conductive vias.

10. The device of claim 5, wherein the interconnect layer comprises a same material as the encapsulant layer.

11. The device of claim 10, wherein the same material is a material selected from a group consisting of liquid crystal polymer and polyphenylene sulfide (PPS).

12. The device of claim 1, further comprising a plurality of interconnect layers coupled to one of the at least two portions of the electrically conductive layer.

13. The device of claim 1, wherein the encapsulant layer comprises an electrically conductive material.

14. The device of claim 1, further comprising a second encapsulant layer overlying the encapsulant layer.

15. The device of claim 1, wherein the encapsulant layer comprises an electrically conductive material.

16. The device of claim 1, further comprising a second circuit device having a first terminal coupled to a first physically separate portion of the electrically conductive layer and having a second terminal coupled to a second physically separate portion of the electrically conductive layer.

17. The device of claim 1, further comprising an interconnect layer overlying the first surfaces of the circuit device and the electrically conductive layer, wherein the second circuit device is electrically coupled to the interconnect layer via the first and second physically separate portions.

18. A device with at least partial packaging, comprising:

a circuit device having a first surface and a second surface opposite the first surface, wherein the first surface comprises active circuitry;

an electrically conductive frame having a first surface, a second surface opposite the first surface, and at least one opening, wherein;

the circuit device is within the at least one opening,

the first surface of the circuit device is substantially coplanar with the first surface of the electrically conductive frame, and

the electrically conductive frame comprises a reference voltage plane;

an electrical contact, electrically coupled to the first reference voltage plane, said electrical contact enabling electrical contact to be made to said first reference voltage plane; and

an encapsulant overlying the second surface of the circuit device and the second surface of the electrically conductive frame, wherein the encapsulant comprises an electrically conductive material.

19. The device of claim 18, further comprising a second circuit device in physical contact with a first portion of the second surface of the electrically conductive layer.

20. The device of claim 19, wherein the second circuit device is selected from a group consisting of a passive device, an optical device, an active device, and a semiconductor device, an antennae, and a micro-electro-mechanical system (MEMS) device.

21. The device of claim 19, wherein the encapsulant layer overlies the second circuit device.

22. The device of claim 18, wherein the electrically conductive layer comprises at least two portions electrically isolated from each other, wherein one of the at least two portions comprises the reference voltage plane.

23. The device of claim 22, further comprising a second circuit device having a first terminal coupled one of the at least two portions and a second terminal coupled to another one of the at least two portions.