Adaptively controlled circuit
First Claim
1. An adaptively controlled circuit comprising:
- an output buffer circuit having inputs and outputs and a bias control input;
a sensing circuit having inputs and outputs of which two or more outputs turn to lower or higher level than a predetermined threshold level at the same time;
a current conversion circuit composed of one or more set of cascaded transistors, of which inputs are connected to outputs of the sensing circuit and the output is connected to foresaid bias control input of the output buffer, wherein a output current of the current conversion circuit increases when signal level of the inputs of the sensing circuit become equal or close each other;
wherein the sensing circuit has two or more differential pair transistors and having a voltage or current width as W sensing window and a response time T(second), and for a transition rate Vc(Volt or ampere/second) of foresaid input of differential pair transistors, in order to realize a relationship W>
Vc*T two of the transistor in foresaid differential pair transistors have different conductance to each other.
1 Assignment
0 Petitions
Accused Products
Abstract
Adaptively controlled circuits are provided that can include an output buffer circuit, a sensing circuit, and a current conversion circuit. The output buffer circuit can include, for example, inputs, outputs and a bias control input. The sensing circuit can also include inputs and outputs. Two or more sensing circuit outputs can simultaneously turn to lower or higher level than a predetermined threshold level. The current conversion circuit can be composed of one or more set of cascaded transistors. Inputs of the cascaded transistors can be connected to outputs of the sensing circuit. The output of the cascaded transistors can be connected to foresaid bias control input of the output buffer. An output current of the current conversion circuit increases when signal level of the inputs of the sensing circuit become equal or close to each other.
13 Citations
4 Claims
-
1. An adaptively controlled circuit comprising:
-
an output buffer circuit having inputs and outputs and a bias control input;
a sensing circuit having inputs and outputs of which two or more outputs turn to lower or higher level than a predetermined threshold level at the same time;
a current conversion circuit composed of one or more set of cascaded transistors, of which inputs are connected to outputs of the sensing circuit and the output is connected to foresaid bias control input of the output buffer, wherein a output current of the current conversion circuit increases when signal level of the inputs of the sensing circuit become equal or close each other;
wherein the sensing circuit has two or more differential pair transistors and having a voltage or current width as W sensing window and a response time T(second), and for a transition rate Vc(Volt or ampere/second) of foresaid input of differential pair transistors, in order to realize a relationship W>
Vc*T two of the transistor in foresaid differential pair transistors have different conductance to each other.
-
-
2. An adaptively controlled circuit comprising:
-
a sensing circuit having inputs and outputs and a bias control input, of which two or more outputs turn to lower or higher level than a predetermined threshold level at the same time;
a current conversion circuit composed of one or more set of cascaded transistors, of which inputs are connected to outputs of the sensing circuit and the output is connected to foresaid bias control input of the sensing circuit, wherein a output current of the current conversion circuit increases when signal level of the inputs of the sensing circuit become equal or close each other;
wherein the sensing circuit has two or more differential pair transistors and having a voltage or current width as W sensing window and a response time T(second), and for a transition rate Vc(Volt or ampere/second) of foresaid input of differential pair transistors, in order to realize a relationship W>
Vc*T two of the transistor in foresaid differential pair transistors have different conductance to each other.
-
-
3. An adaptively controlled circuit comprising:
-
an output buffer circuit having inputs and outputs and a bias control input;
a sensing circuit having inputs and outputs and a bias control input, of which two or more outputs turn to lower or higher level than a predetermined threshold level at the same time;
a current conversion circuit composed of one or more set of cascaded transistors, of which inputs are connected to outputs of the sensing circuit and one of output is connected to foresaid bias control input of the output buffer, and other output is connected to the bias control input of the sensing circuit, wherein output current of the current conversion circuit increases when signal level of the inputs of the sensing circuit become equal or close each other;
wherein the sensing circuit has two or more differential pair transistors and having a voltage or current width as W sensing window and a response time T(second), and for a transition rate Vc(Volt or ampere/second) of foresaid input of differential pair transistors, in order to realize a relationship W>
Vc*T two of the transistor in foresaid differential pair transistors have different conductance to each other.
-
-
4. An adaptively controlled circuit comprising:
-
an output buffer circuit having inputs and outputs a bias control input;
a sensing circuit having inputs and outputs and a bias control input, of which two or more outputs turn to lower or higher level than a predetermined threshold level at the same time;
a bias current generation circuit having one current mirror output at least, which is connected to said bias control input of the sensing circuit and/or the buffer circuit, a current conversion circuit composed of one or more set of cascaded transistors, of which inputs are connected to the outputs of the sensing circuit and one of output is connected to foresaid bias current generation circuit, wherein output current of the current conversion circuit increases when signal level of the inputs of the sensing circuit become equal or close each other;
wherein the sensing circuit has two or more differential pair transistors and having a voltage or current width as W sensing window and a response time T(second), and for a transition rate Vc(Volt or ampere/second) of foresaid input of differential pair transistors, in order to realize a relationship W>
Vc*T two of the transistor in foresaid differential pair transistors have different conductance to each other.
-
Specification