Method and apparatus for vector processing
First Claim
Patent Images
1. An apparatus (302) for performing dynamically scalable single instruction multiple data (SIMD) operations comprising:
- a first vector arithmetic logic unit (402) operably coupled to a first data vector (VRA) from a first input data bus, a second data vector (VRB) from a second vector data bus, and a third data vector (VRC) from a third vector data bus to produce a first vector result (VRD) wherein the first vector functional arithmetic logic unit (402) performs individual conditional operations on fields of VRA and VRB to produce VRD, and wherein the conditional operations are based on VRC;
a second vector arithmetic logic unit (401) operably coupled to the first data vector (VRA) from the first input data bus, the second data vector (VRB) from the second input data bus, and to the first vector arithmetic logic unit, wherein the individual conditional vector operations in the first vector arithmetic logic unit are conditionally controlled by a vector result from the second vector arithmetic logic unit.
2 Assignments
0 Petitions
Accused Products
Abstract
A processor includes a first vector processing unit including a first register file and first vector arithmetic logic unit; a second vector processing unit including a second register file and second vector arithmetic logic unit wherein the first register file has a first plurality of cross connections to the second vector arithmetic logic unit; wherein the second register file as a second plurality of cross connections to the first vector arithmetic logic unit.
61 Citations
12 Claims
-
1. An apparatus (302) for performing dynamically scalable single instruction multiple data (SIMD) operations comprising:
-
a first vector arithmetic logic unit (402) operably coupled to a first data vector (VRA) from a first input data bus, a second data vector (VRB) from a second vector data bus, and a third data vector (VRC) from a third vector data bus to produce a first vector result (VRD) wherein the first vector functional arithmetic logic unit (402) performs individual conditional operations on fields of VRA and VRB to produce VRD, and wherein the conditional operations are based on VRC;
a second vector arithmetic logic unit (401) operably coupled to the first data vector (VRA) from the first input data bus, the second data vector (VRB) from the second input data bus, and to the first vector arithmetic logic unit, wherein the individual conditional vector operations in the first vector arithmetic logic unit are conditionally controlled by a vector result from the second vector arithmetic logic unit. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. An apparatus (302) for performing dynamically scalable SIMD operations, the apparatus (302) comprising:
-
a first vector arithmetic unit (402) having a first, second, and third data vector as inputs, the first vector arithmetic unit capable of performing at least vector addition and subtraction operations, wherein individual SIMD field operations in the first vector arithmetic unit are conditionally controlled by at least a portion of the third data vector input; and
a second vector arithmetic unit (401) operably coupled to the first vector arithmetic unit. - View Dependent Claims (8, 9, 10, 11, 12)
-
Specification