Method and apparatus for handling locks

• US 6,922,745 B2
• Filed: 05/02/2002
• Issued: 07/26/2005
• Est. Priority Date: 05/02/2002
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kumar, Harish, Zhang, Zhongying, Upton, Mike D., Hum, Herbert H., Venkatraman, KS, Baktha, Aravindh
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US10/139,215
• Publication Number:
  US 20030208647A1
• Time in Patent Office: 1,181 Days
• Field of Search: 710/200, 711/145, 711/163
• US Class Current: 710/200
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences associated with multiple threads of a processing device.

Claims

1. A method comprising:

selecting a first lock protocol if a lock is associated with a first memory type; and

selecting a second lock protocol if the lock is associated with a second memory type.

2. The method of claim 1, further comprising performing the selected lock protocol.

3. The method of claim 1, wherein the first memory type corresponds to an address that is cacheable and the second memory type corresponds to an address that is not cacheable.

4. A method comprising:

determining whether a memory type is associated with a locked μ

OP;

if the memory type is associated with the locked μ

OP, selecting a first lock protocol; and

if the memory type is not associated with the locked μ

OP, selecting a second lock protocol.

5. The method of claim 4, further comprising tagging the locked μ

OP as a first lock type if the memory type is associated with the locked μ

OP.

6. The method of claim 5, further comprising tagging the locked μ

OP as a second lock type if the memory type is not associated with the locked μ

OP.

7. The method of claim 4, wherein the memory type corresponds to a memory address that is cacheable or a memory address that is not cacheable.

8. A method comprising:

determining whether a locked μ

OP is cacheable;

if the locked μ

OP is cacheable, selecting a cache lock protocol; and

if the locked μ

OP is not cacheable, selecting a bus lock protocol.

9. The method of claim 8, further comprising tagging the locked μ

OP as a cache lock if the locked μ

OP is cacheable.

10. The method of claim 9, further comprising tagging the locked μ

OP as a bus lock if the locked μ

OP is not cacheable.

11. A method comprising:

accessing a locked μ

OP;

selecting a lock protocol in response to a memory type associated with the locked μ

OP; and

executing the selected lock protocol.

12. The method of claim 11, wherein the locked μ

OP, when accessed, is being replayed in a replay loop.

13. The method of claim 11, wherein the lock protocol is selected from a cache lock protocol and a bus lock protocol.

14. The method of claim 11, wherein the memory type corresponds to a memory address that is cacheable or a memory address that is not cacheable.

15. The method of claim 11, further comprising performing a lock sequence.

16. A device comprising:

a local bus; and

a protocol selection unit coupled with the local bus, the protocol selection unit to

select a first lock protocol if a lock is associated with a first memory type; and

select a second lock protocol if the lock is associated with a second memory type.

17. The device of claim 16, wherein the first memory type corresponds to an address that is cacheable and the second memory type corresponds to an address that is not cacheable.

18. The device of claim 16, further comprising a memory cluster, the protocol selection unit coupled with the memory cluster.

19. The device of claim 18, wherein the memory cluster includes a cache memory.

20. A device comprising:

a local bus; and

a protocol selection unit coupled with the local bus, the protocol selection unit to

determine whether a memory type is associated with a locked μ

OP;

if the memory type is associated with the locked μ

OP, select a first lock protocol; and

if the memory type is not associated with the locked μ

OP, select a second lock protocol.

21. The device of claim 20, the protocol selection unit to tag the locked μ

OP as a first lock type if the memory type is associated with the locked μ

OP.

22. The device of claim 21, the protocol selection unit to tag the locked μ

OP as a second lock type of the memory type is not associated with the locked μ

OP.

23. The device of claim 20, wherein the a memory type corresponds to a memory address that is cacheable or a memory address that is not cacheable.

24. The device of claim 20, further comprising a memory cluster, the protocol selection unit coupled with the memory cluster.

25. The device of claim 24, wherein the memory cluster includes a cache memory.

26. An article of manufacture comprising:

a medium having content that, when accessed by a device, causes the device to

select a first lock protocol if a lock is associated with a first memory type; and

select a second lock protocol if the lock is associated with a second memory type.

27. The article of manufacture of claim 26, wherein the content, when accessed, further causes the device to perform the selected lock protocol.

28. The article of manufacture of claim 27, wherein the first memory type corresponds to an address that is cacheable and the second memory type corresponds to an address that is not cacheable.

29. An article of manufacture comprising:

a medium having content that, when accessed by a device, causes the device to

determine whether a memory type is associated with a locked μ

OP;

if the memory type is associated with the locked μ

OP, select a first lock protocol; and

if the memory type is not associated with the locked μ

OP, select a second lock protocol.

30. The article of manufacture of claim 29, wherein the content, when accessed, further causes the device to tag the locked μ

OP as a first lock type if the memory type is associated with the locked μ

OP.

31. The article of manufacture of claim 30, wherein the content, when accessed, further causes the device to tag the locked μ

OP as a second lock type if the memory type is not associated with the locked μ

OP.

32. The article of manufacture of claim 39, wherein the memory type corresponds to a memory address that is cacheable or a memory address that is not cacheable.