System and a method for checking lock step consistency between an in circuit emulation and a microcontroller while debugging process is in progress

• US 6,922,821 B1
• Filed: 11/15/2001
• Issued: 07/26/2005
• Est. Priority Date: 11/15/2001
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Nemecek, Craig
• Primary Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US09/998,859
• Time in Patent Office: 1,349 Days
• Field of Search: 716/4, 703/13, 703/14, 717/128
• US Class Current: 716/136
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

Checking the consistency of a lock step process while debugging a microcontroller code is in progress. A method provides a production microcontroller to execute an instruction code and provides the result of the instruction code to an ICE. The ICE, independent from the production microcontroller and simultaneously, executes the same instruction code and produces a result. The ICE compares the result of its computation and the result received from the production microcontroller. The ICE issues a “lock step error” when the result of the comparison is a mismatch. A trace buffer residing in the host device provides the location of the line of code causing the mismatch. After identifying the line of code causing the mismatch the user debugs the erroneous line of code. The debugging process resumes on the next line of code in the microcontroller code under test.

Claims

1. A system for check consistency of a lock-step process comprising:

a production microcontroller installed on a test circuit, the production microcontroller running a microcontroller code and producing a first value;

an ICE (in circuit emulator) coupled to a host device, wherein the ICE emulates the production microcontroller to form a virtual microcontroller, the virtual microcontroller running the microcontroller code simultaneously with the production microcontroller and producing a second value; and

an interface for coupling the production microcontroller and the ICE enabling transmission of the first value to the ICE, where the production microcontroller sends to the ICE a result of an execution of a line of code, and wherein the ICE compares the first value against the second value.

2. A system for checking consistency of a lock-step process as recited in claim 1 wherein the production microcontroller is installed on a pod.

3. A system for checking consistency of a lock-step process as recited in claim 1 wherein the production microcontroller is substantially copied in a field programmable gate array (FPGA) in the ICE.

4. A system for checking consistency of a lock-step process as recited in claim 1 where the ICE ignores execution of the microcontroller code if the microcontroller code executed by the virtual microcontroller is an I/O instruction.

5. A system for checking consistency of a lock-step process as recited in claim 1 where the ICE ignores execution of the microcontroller code if there is an interrupt in operation of the production microcontroller.

6. A system for checking consistency of a lock-step process as recited in claim 1 wherein the ICE stores the second value for comparison with the first value received from the production microcontroller.

7. A system for checking consistency of a lock-step process as recited in claim 1 wherein the ICE sends an error signal when the first value and the second value are inconsistent.

8. A system for checking consistency of a lock-step process as recited in claim 1 wherein the ICE independently detects inconsistency in the first value and the second value when there is an interrupt in operation of the production microcontroller.

9. A system for checking consistency of a lock-step process as recited in claim 1 wherein the production microcontroller receives data from a test circuit.

10. A system for checking consistency of a lock-step process as recited in claim 1 wherein the production microcontroller receives data from a product controlled by the production microcontroller.

11. A system for checking consistency of a lock-step process as recited in claim 1 wherein the production microcontroller provides the ICE with I/O read information sent by the test circuit.

12. A system for checking consistency of a lock-step process as recited in claim 1 wherein the production microcontroller provides the ICE with I/O read information sent by a product controlled by the production microcontroller.

13. A system for checking consistency of a lock-step process as recited in claim 1, wherein the ICE compares the first and the second values and where there is inconsistency a software residing in the ICE halts the execution of the microcontroller code and issues an error signal.

14. A method for verifying lock step microcontroller code execution in a code debugging process comprising:

a) initializing a first memory of an ICE (in circuit emulator) and a second memory of a microcontroller with microcontroller test code;

b) executing the microcontroller test code on the microcontroller and on the ICE in lock step;

c) computing an ICE current instruction result and a microcontroller current instruction result;

d) verifying lock step execution by comparing the ICE current instruction result and the microcontroller current instruction result;

d) if lock step execution is not verified, halting the execution of the microcontroller test code and reporting an error; and

e) if lock step execution is verified, continuing execution of the microcontroller test code.

15. The method of claim 14 further comprising:

if lock step execution is not verified, saving an execution history using a trace buffer coupled to the ICE.

16. The method of claim 14 further comprising:

transmitting the microcontroller current instruction result from the microcontroller to the ICE for verifying the lock step execution.

17. The method of claim 14 wherein the ICE ignores execution of an instruction if the instruction is an I/O instruction.

18. The method of claim 14 wherein the ICE ignores execution of an instruction if the instruction is an interrupt.

19. The method of claim 14 wherein the ICE independently detects inconsistency between the ICE current instruction result and the microcontroller current instruction result when the execution of the microcontroller test code is halted.

20. A lock step code execution microcontroller testing system comprising:

a microcontroller installed on a test circuit, the microcontroller running microcontroller code, the microcontroller installed on a pod;

an ICE (in circuit emulator) coupled to a host device, wherein the ICE emulates the microcontroller using a field programmable gate array (FPGA) in the ICE, the ICE running the microcontroller code simultaneously with the microcontroller; and

an interface for coupling the microcontroller and the ICE enabling data transmission between the ICE and the microcontroller, wherein the ICE compares a microcontroller execution result with an ICE execution result to verify lock step microcontroller code execution.

21. The system of claim 20 wherein the ICE ignores execution of the microcontroller code if the microcontroller code executed by the microcontroller is an I/O instruction.

22. The system of claim 20 wherein the ICE ignores execution of the microcontroller code if the microcontroller code is an interrupt instruction.

23. The system of claim 20 wherein the ICE independently detects inconsistency between the microcontroller execution result and the ICE execution result when there is a halt in the operation of the microcontroller.

24. The system of claim 20 wherein the microcontroller is coupled to receive data from a product controlled by the microcontroller.

25. The system of claim 20 wherein the microcontroller provides the ICE with I/O read information sent by a product controlled by the microcontroller.