Method of forming a pocket implant region after formation of composite insulator spacers

• US 6,924,180 B2
• Filed: 02/10/2003
• Issued: 08/02/2005
• Est. Priority Date: 02/10/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Quek, Elgin
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Pham, Thanh V.
• Application Number:
  US10/361,934
• Publication Number:
  US 20040157397A1
• Time in Patent Office: 904 Days
• Field of Search: 438/163, 438/174, 438/185, 438/194, 438/217, 438/231, 438/232, 438/303
• US Class Current: 438/163
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A process for forming a MOSFET device featuring a pocket region placed adjacent to only a top portion of the sides of a heavily doped source/drain region, has been developed. The process features forming a heavily doped source/drain region in an area of a semiconductor substrate not covered by the gate structure or by composite insulator spacers located on the sides of the gate structure. Selective removal of an overlying insulator component of the composite insulator spacer allows a subsequent pocket implant region to be formed in an area of the semiconductor substrate directly underlying a horizontal portion of a remaining L shaped insulator spacer component. The location of the pocket region, formed butting only the top portions of the sides of the heavily doped source/drain region, reduces the risk of punch through current while limiting the impact of junction capacitance.

Claims

1. A method of forming a metal oxide semiconductor field effect transistor (MOSFET), on a semiconductor substrate, featuring formation of a combination of two pocket implant regions, one completely surrounding a lightly doped source/drain region and the other formed adjacent to the sides of a heavily doped source/drain region, comprising the steps of:

providing a gate insulator layer on a semiconductor substrate comprised with a first conductivity type, with a gate structure overlying said gate insulator layer;

forming a said lightly doped source/drain (LDD) region of a second conductivity type, in portion of said semiconductor substrate not covered by said gate structure;

forming first pocket region of a first conductivity type in a portion of said semiconductor substrate not covered by said gate structure, with said first pocket region completely surrounding said LDD region, and wherein said first pocket region, completely enclosing said LDD region, is comprised with a dopant level greater than the dopant level of said semiconductor substrate;

forming a composite insulator spacer on sides of said gate structure, with said composite insulator spacer comprised of an underlying L shaped insulator component, and comprised of an overlying insulator component;

forming said heavily doped source/drain region of a second conductivity type, in a portion of said semiconductor substrate not covered by said gate structure or by said composite insulator spacer;

removing said overlying insulator component of said composite insulator spacer; and

forming a second pocket region of a first conductivity type in a portion of said semiconductor substrate underlying horizontal portion of L shaped insulator component and adjacent to sides of said heavily doped source/drain region, with said second pocket region comprised with a dopant level greater than the dopant level of said first pocket region.

2. The method of claim 1, wherein said semiconductor substrate is a P type semiconductor substrate.

3. The method of claim 1, wherein said gate insulator layer is a silicon dioxide gate insulator, obtained via thermal oxidation procedures to a thickness between about 10 to 20 Angstroms.

4. The method of claim 1, wherein said gate structure is comprised of doped polysilicon or metal silicide.

5. The method of claim 1, wherein the width of said gate structure is between about 0.03 to 0.50 um.

6. The method of claim 1, wherein said lightly doped source/drain region is an N type, lightly doped source/drain region, obtained via implantation of arsenic or phosphorous ions, at an implant energy between about 1 to 10 KeV, and at an implant dose between about 3E15 to 5E15 atoms/cm².

7. The method of claim 1, wherein said first pocket region is a P type pocket region, obtained via implantation of boron or BF₂ ions, at an implant energy between about 7 to 15 KeV, and at an implant dose between about 2E13 to 7E13 atoms/cm².

8. The method of claim 1, wherein said underlying L shaped insulator component of said composite insulator spacer is comprised of silicon nitride, at a thickness between about 150 to 300 Angstroms.

9. The method of claim 1, wherein said composite insulator spacer is defined via an anisotropic RIE procedure applied to an overlying silicon oxide layer using CHF₃ as an etchant, and applied to an underlying silicon nitride layer using Cl₂ as an etchant.

10. The method of claim 1, wherein said overlying insulator component of said composite insulator spacer is comprised of silicon oxide, at a thickness between about 400 to 700 Angstroms.

11. The method of claim 1, wherein silicon oxide of said overlying insulator component of said composite insulator spacer, is obtained via LPCVD or PECVD procedures, using tetraethylorthosilicate (TEOS), as a source.

12. The method of claim 1, wherein said heavily doped source/drain region is a heavily doped N type source/drain region, obtained via implantation of arsenic or phosphorous ions, at an implant energy between about 35 to 75 KeV, and at an implant dose between about 2E15 to 7E15 atoms/cm², followed by an additional procedure performed via implantation of phosphorous ions at an energy between about 25 to 45 KeV, at a dose between about 1E13 to 4E13, using an implant angle between about 0 to 7°

.

13. The method of claim 1, wherein said overlying insulator component is removed via a selective wet etch procedure, using a buffered hydrofluoric acid solution.

14. The method of claim 1, wherein said second pocket region is a P type pocket region, obtained via implantation of boron or BF₂ ions, at an implant energy between about 21 to 31 KeV, and at an implant dose between about 3E13 to 8E13 atoms/cm², using an implant or tilt angle between about 10 to 30°

.

15. A method of forming a metal oxide semiconductor field effect transistor (MOSFET), on a semiconductor substrate, featuring formation of a combination of pocket implant regions, with a second pocket region comprised of a deep P type pocket region formed after heavily doped source/drain and composite insulator spacer formation, comprising the steps of:

forming silicon dioxide gate insulator layer on a P type semiconductor substrate;

forming conductive gate structure on said silicon dioxide gate insulator layer;

forming N type, lightly doped source/drain (LDD) region in a portion of said P type semiconductor substrate not covered by said conductive gate structure;

forming a first pocket region, a shallow, P type pocket region formed in an area of said P type semiconductor substrate not covered by said conductive gate structure, with said shallow, P type pocket region completely surrounding and enclosing said N type LDD region, and wherein said shallow, P type pocket region is comprised with a P type dopant level greater than the P type dopant level of said P type semiconductor substrate;

forming a silicon nitride layer;

forming a silicon oxide layer;

performing an anisotropic reactive ion etch procedure to form a composite insulator spacer on sides of said conductive gate structure, with said composite insulator spacer comprised of an underlying L shaped silicon nitride component, and comprised of an overlying silicon oxide component;

forming a heavily doped N type source/drain region in an area of said P type semiconductor substrate not covered by said conductive gate structure or by said composite insulator spacer;

removing said overlying silicon oxide component of said composite insulator spacer;

forming said second pocket region, said deep, P type pocket region, formed using an implantation angle between about 10 to 30°

in a portion of said P type semicondutor substrate underlying a horizontal portion of said L shaped silicon nitride insulator component of said composite insulator spacer, with said deep, P type pocket region comprised with a P type dopant level greater than the P type dopant level of said shallow pocket region; and

performing an anneal procedure.

16. The method of claim 15, wherein said silicon dioxide gate insulator layer is obtained at thickness between about 10 to 20 Angstroms, via a thermal oxidation procedure performed in an oxygen—

steam ambient.

17. The method of claim 15, wherein said conductive gate structure is comprised of doped polysilicon, or metal silicide.

18. The method of claim 15, wherein said conductive gate structure is comprised with a width between about 0.03 to 0.50 um.

19. The method of claim 15, wherein said N type lightly doped source/drain region is obtained via implantation of arsenic or phosphorous ions, at an implant energy between about 1 to 10 KeV, and at an implant dose between about 3E13 to3E15 atoms/cm².

20. The method of claim 15, wherein said shallow, P type pocket region is obtained via implantation of boron or BF₂ ions, at an implant energy between about 7 to 15 KeV, and at an implant dose between about 2E13 to 7E13 atoms/cm².

21. The method of claim 15, wherein said silicon nitride layer is obtained via LPCVD or PECVD procedures, at a thickness between about 150 to 300 Angstroms.

22. The method of claim 15, wherein said silicon oxide layer is obtained via LPCVD or PECVD procedures, at a thickness between about 400 to 700 Angstroms, using tetraethylorthosilicate (TEOS), as a source.

23. The method of claim 15, wherein said anisotropic reactive ion etch procedure used to define said composite insulator spacer, is performed using CHF₃ as an etchant for said silicon oxide layer, and using Cl₂ as an etchant for said silicon nitride layer.

24. The method of claim 15, wherein said heavily doped N type source/drain region is obtained via implantation of arsenic or phosphorous ions, at an implant energy between about 35 to 75 KeV, and at an implant dose between about 2E15 to 7E15 atoms/cm², followed by an additional procedure performed via implantation of phosphorous ions at an energy between about 25 to 45 KeV, at a dose between about 1E13 to 4E13, using an implant angle between about 0 to 7°

.

25. The method of claim 15, wherein said overlying silicon oxide component of said composite insulator spacer, is removed via a selective wet etch procedure using a buffered hydrofluoric acid solution.

26. The method of claim 15, wherein said deep, P type pocket region is obtained via implantation of boron or BF₂ ions, at an implant energy between about 21 to 31 KeV, and at an implant dose between about 3E13 to 8E13 atoms/cm², using an implant or tilt angle between about 10 to 30°

.

27. The method of claim 15, wherein said anneal procedure is a rapid thermal anneal RTA), procedure, performed at a temperature between about 1050 to 1090°

C., for a time between about 0 to 15 sec, in an inert ambient.