Method for fabricating a gate structure of a field effect transistor

• US 6,924,191 B2
• Filed: 06/16/2003
• Issued: 08/02/2005
• Est. Priority Date: 06/20/2002
• Status: Expired due to Term

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Liu, Wei, Lill, Thorsten B., Bencher, Christopher Dennis, Mui, David S. L.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Yevsikov, Victor V
• Application Number:
  US10/463,460
• Publication Number:
  US 20040043623A1
• Time in Patent Office: 778 Days
• Field of Search: 438/241, 438/328, 438/275, 438/595, 438/182, 438/270, 438/257, 438/694
• US Class Current: 438/241
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

A method for fabricating features on a substrate having reduced dimensions. The features are formed by defining a first mask on regions of the substrate. The first mask is defined using lithographic techniques. A second mask is then conformably formed on one or more sidewalls of the first mask. The features are formed on the substrate by removing the first mask and then etching the substrate using the second mask as an etch mask.

Claims

1. A method of defining a feature on a substrate, comprising:

(a) providing a substrate having a material layer formed thereon;

(b) forming a first mask comprising amorphous carbon on the material layer;

(c) forming a second mask conformably on one or more sidewalls of the first mask to a thickness defining a smallest width of the feature;

(d) removing the first mask using a plasma comprising at least one of hydrogen bromide (HBr) and oxygen (O₂); and

(e) plasma etching the material layer using the second mask as an etch mask to define at least one feature therein.

2. The method of claim 1 wherein step (b) further comprises:

(b1) depositing an amorphous carbon layer on the material layer;

(b2) forming a photoresist pattern on the amorphous carbon layer;

(b3) transferring the photoresist pattern into the amorphous carbon layer; and

(b4) removing the photoresist pattern.

3. The method of claim 1 wherein the first mask further comprises a dielectric antireflective coating (DARC).

4. The method of claim 1 wherein step (c) further comprises:

(c1) depositing a second mask layer conformably over the first mask;

(c2) removing portions of the second mask layer disposed on horizontal surfaces of the first mask and the substrate using a plasma etch process having an overetch period;

(c3) forming over the second mask layer a photoresist pattern exposing first regions of the second mask layer;

(c4) removing the first region of the second mask layer to form the second mask; and

(c5) removing the photoresist pattern.

5. The method of claim 1 the first mask further comprises a dielectric antireflective coating (DARC).

6. The method of claim 1 wherein the material layer comprises polysilicon.

7. A method of fabricating a gate structure of a field effect transistor comprising:

(a) providing a substrate having a gate electrode layer formed on a gate dielectric layer;

(b) forming a first mask comprising amorphous carbon on regions of the gate layer above source, drain, and channel regions of the transistor;

(c) forming a second mask conformably on one or more sidewalls of the first mask to a thickness defining a length of the channel region;

(d) removing the first mask using a plasma comprising at least one of hydrogen bromide (HBr) and oxygen (O₂); and

(e) completing the gate structure by plasma etching the gate electrode layer and the gate dielectric layer using the second mask as an etch mask.

8. The method of claim 7 wherein step (b) further comprises:

(b1) depositing an amorphous carbon layer on the material layer;

(b2) forming a photoresist pattern on the amorphous carbon layer;

(b3) transferring the photoresist pattern into the amorphous carbon layer; and

(b4) removing the photoresist pattern.

9. The method of claim 7 wherein the first mask comprises a dielectric antireflective coating (DARC) formed from at least one of silicon oxynitride (SlON) and silicon dioxide (SiO₂).

10. The method of claim 7 wherein step (c) further comprises:

(c1) depositing a second mask layer conformably over the first mask;

(c2) removing portions of the second mask layer disposed on horizontal surfaces of the first mask and the substrate using a plasma etch process having an overetch period;

(c3) forming over the second mask layer a photoresist pattern exposing first regions of the second mask layer;

(c4) removing the first regions of the second mask layer to form the second mask; and

(c5) removing the photoresist pattern.

11. The method of claim 7 wherein the second mask comprises a material selected from the group consisting of silicon dioxide (SiO₂) and silicon nitride (Si₃N₄).

12. The method of claim 7 wherein the gate electrode layer comprises polysilicon.

13. The method of claim 7 wherein the gate electrode layer comprises one or more films of at least one of silicon dioxide (SiO₂), hafnium silicon dioxide (HfSiO₂), and aluminum oxide (Al₂O₃).

14. A method of fabricating a field effect transistor on a substrate comprising:

(a) providing a substrate having a gate electrode layer formed an a gate dielectric layer;

(b) forming a first mask comprising amorphous carbon on regions of the gate electrode layer above source drain, and channel regions of the transistor;

(c) forming a second mask conformably on one or more sidewalls of the first mask to a thickness defining a length of the channel region;

(d) removing the first mask using a plasma comprising at least one of hydrogen bromide (HBr) and oxygen (O₂); and

(e) completing the gate structure by plasma etching the gate electrode layer and the gate dielectric layer using the second mask as an etch mask.

15. The method of claim 14 wherein step (b) further comprises:

(b1) depositing an amorphous carbon layer on the material layer;

(b2) forming a photoresist pattern on the amorphous carbon layer;

(b3) transferring the photoresist pattern into the amorphous carbon layer; and

(b4) removing the photoresist pattern.

16. The method of claim 14 wherein the first mask further comprises a dielectric antireflective coating (DARC) formed from at least one of silicon oxynitride (SiON) and silicon dioxide (SiO₂).

17. The method of claim 14 wherein step (c) further comprises:

(c1) depositing a second mask layer conformably over the first mask;

(c2) removing portions of the second mask layer disposed on horizontal surfaces of the first mask and the substrate using a plasma etch process having an overetch period;

(c3) forming over the second mask layer a photoresist pattern exposing first regions of the second mask layer;

(c4) removing the first regions of the second mask layer to form the second mask; and

(c5) removing the photoresist pattern.

18. The method of claim 14 wherein the second mask comprises a material selected from the group consisting of silicon dioxide (SiO₂) and silicon nitride (Si₃N₄).

19. The method of claim 14 wherein the gate electrode layer comprises polysilicon.

20. The method of claim 14, wherein the gate electrode layer comprises one or more films of at least one of silicon dioxide (SiO₂), hafnium silicon dioxide (HfSiO₂), and aluminum oxide (Al₂O₃).