DRAM technology compatible processor/memory chips

• US 6,924,194 B2
• Filed: 07/09/2002
• Issued: 08/02/2005
• Est. Priority Date: 02/26/1999
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P., Cloud, Eugene H.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HOANG, QUOC DINH
• Application Number:
  US10/191,330
• Publication Number:
  US 20020176293A1
• Time in Patent Office: 1,120 Days
• Field of Search: 438/253, 438/257, 438/258, 438/266
• US Class Current: 438/253
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H03K 19/17716 with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register H03K19/17712 takes precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Claims

1. A method for forming a DRAM/EEPROM chip, comprising:

forming a plurality of dynamic random access memory (DRAM) access transistors on a semiconductor substrate;

forming a plurality of stacked capacitors in a subsequent level above the plurality of DRAM access transistors and separated from the plurality of DRAM access transistors by an insulator layer;

coupling a first group of the plurality of stacked capacitors, with a coupling ratio greater than 1.0, to a gate for each DRAM access transistor in a first group of the plurality of DRAM access transistors; and

coupling a second group of the plurality of stacked capacitors to a diffused region in a second group of the plurality of DRAM access transistors.

2. The method of claim 1, wherein forming a plurality of DRAM access transistors includes forming a plurality of n-channel metal oxide semiconductor (NMOS) transistors.

3. The method of claim 1, wherein forming a plurality of stacked capacitors includes forming a plurality of stacked capacitors having a bottom plate, a capacitor dielectric, and a top plate, wherein the bottom plate is formed in a cup shape having interior walls, the capacitor dielectric is formed conformal to the bottom plate and the top plate is formed conformal to the capacitor dielectric, and wherein forming the plurality of stacked capacitors includes forming a portion of the top plate within the interior walls of the bottom plate.

4. The method of claim 3, wherein coupling a first group of the plurality of stacked capacitors to a gate in each DRAM access transistors in a first group of the plurality of DRAM access transistors includes coupling the bottom plate of each stacked capacitor in the first group of the plurality of stacked capacitors to the gate for the first group of the plurality of DRAM access transistors.

5. The method of claim 1, wherein the forming a plurality of stacked capacitors includes forming the plurality of stacked capacitors according to a dynamic random access memory (DRAM) process flow.

6. A method for forming an integrated circuit, the method comprising:

forming a plurality of metal oxide semiconductor transistors (MOSFETs) in and on a layer of semiconductor material;

forming a first set of stacked capacitors that are coupled to diffusion regions of selected ones of the plurality of MOSFETs to form a memory array; and

forming, on the same layer of semiconductor material, a second set of stacked capacitors, with a coupling ratio greater than 1.0, that are coupled to gates of selected ones of the plurality of MOSFETs to form a plurality of non-volatile memory cells; and

interconnecting the memory array and the non-volatile memory cells to provide the integrated circuit.

7. The method of claim 6, wherein forming a second set of stacked capacitors comprises forming a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form a EEPROM.

8. The method of claim 6, wherein forming a second set of stacked capacitors comprises forming a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form at least one programmable logic array.

9. The method of claim 6, wherein forming a second set of stacked capacitors comprises forming a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form a memory decode array.

10. The method of claim 6, wherein forming a second set of stacked capacitors comprises forming a second set of stacked capacitors that are coupled to gates of selected ones of the plurality of MOSFETs to form at least one programmable logic array of a processor circuit.

11. A method for forming a memory chip, comprising:

forming a plurality of access transistors at a first level of a substrate;

forming a plurality of stacked capacitors at a second level of the substrate;

forming an insulator separating the plurality of access transistors from the plurality of stacked capacitors;

coupling a first group of the plurality of stacked capacitors, with a coupling ratio greater than 1.0, to a gate of each access transistor in a first group of the plurality of access transistors; and

coupling a second group of the plurality of stacked capacitors to a first region in a second group of the plurality of access transistors.

12. The method of claim 11, wherein forming the plurality of access transistors includes forming metal oxide semiconductor transistors.

13. The method of claim 12, wherein forming metal oxide semiconductor transistors includes forming an n-channel transistor.

14. The method of claim 11, wherein forming the stacked capacitors occurs after forming the access transistors.

15. The method of claim 11, wherein the second level is formed above the first level.

16. The method of claim 11, wherein forming a plurality of stacked capacitors includes forming a plurality of stacked capacitors having a bottom plate, a capacitor dielectric, and a top plate, wherein the bottom plate is formed in a cup shape having interior walls, the capacitor dielectric is formed conformal to the bottom plate and the top plate is formed conformal to the capacitor dielectric, and wherein forming the plurality of stacked capacitors includes forming a portion of the top plate within the interior walls of the bottom plate.

17. The method of claim 16, wherein coupling a first group of the plurality of stacked capacitors to a gate in each access transistors in a first group of the plurality of access transistors includes coupling the bottom plate of each stacked capacitor in the first group of the plurality of stacked capacitors to the gate for the first group of the plurality of access transistors.

18. The method of claim 11, wherein forming the plurality of access transistors includes forming a plurality of DRAM access transistors.

19. A method for forming a memory chip, comprising:

forming a plurality of access transistors at a first level of a substrate;

forming a first plurality of first stacked capacitors at a second level of the substrate;

forming a second plurality of second stacked capacitors, with coupling ratios greater than 1.0, on the substrate;

coupling the first plurality of the first stacked capacitors to diffusion regions of selected first ones of the access transistors to form a memory array;

coupling the second plurality of the second stacked capacitors to gates of selected second ones of the access transistors to form a plurality of non-volatile memory cells; and

interconnecting the memory array and the non-volatile memory cells.

20. The method of claim 19, wherein forming the second plurality of second stacked capacitors includes forming the second stacked capacitors includes forming the second stacked capacitors at the second level of the substrate.

21. The method of claim 20, wherein the second level is above the first level.

22. The method of claim 19, wherein forming the plurality of access transistors includes forming metal oxide semiconductor transistors.

23. The method of claim 19, wherein coupling the second plurality of the second stacked capacitors includes forming an EEPROM.

24. The method of claim 19, wherein coupling the second plurality of the second stacked capacitors includes forming a programmable logic array.

25. The method of claim 19, wherein coupling the second plurality of the second stacked capacitors includes forming a memory decode array.

26. The method of claim 19, wherein coupling the second plurality of the second stacked capacitors includes forming at least one programmable logic array of a processor.

27. The method of claim 19, wherein forming the plurality of access transistors includes forming DRAM access transistors.

28. A method of forming an integrated circuit, comprising:

forming an array of intersecting address lines and output lines;

disposing non-volatile memory cells at intersections of the address lines and the output lines;

wherein disposing non-volatile memory cells includes;

forming an access transistor;

forming a stacked capacitor that has a coupling ratio greater than 1.0 and that is coupled to the access transistor; and

selectively programming the non-volatile memory cells to implement a logic function.

29. The method of claim 28, wherein selectively programming includes programming the logic function to select an output line based on an address provided on the address lines.

30. The method of claim 28, wherein forming the array includes forming pairs of an address line and a complementary address line.

31. The method of claim 28, wherein forming the array includes forming N address lines and forming 2^N output lines.

32. The method of claim 28, wherein forming the array includes forming a number of complementary address lines that are each coupled to one of the address lines through an invertor.

33. The method of claim 28, wherein forming the stacked capacitor includes forming a cup-shaped capacitor.

34. The method of claim 28, wherein forming the stacked capacitor includes forming capacitors according to a DRAM process.

35. The method of claim 28, wherein forming the stacked capacitor includes connecting the capacitors to a gate of the access transistor.

36. The method of claim 35, wherein connecting the capacitors includes connecting the capacitors to the gate with a polysilicon plug.

37. The method of claim 28, wherein forming the capacitor includes forming a fin type capacitor.

38. A method for forming a dual memory chip, comprising:

forming a plurality of random access memory access transistors on a semiconductor substrate;

forming a plurality of stacked capacitors in a subsequent level above the plurality of random access memory access transistors and separated form the plurality of random access memory access transistors by an insulator layer; and

coupling a first group of the plurality of stacked capacitors, with a coupling ratio greater than 1.0, to a gate for each random access memory access transistor in a first group of the plurality of random access memory access transistors;

coupling a second group of the plurality of stacked capacitors to a diffused region in a second group of the plurality of random access memory access transistors.