Self-aligned trench transistor using etched contact

• US 6,924,198 B2
• Filed: 01/28/2004
• Issued: 08/02/2005
• Est. Priority Date: 04/22/1999
• Status: Expired due to Term

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Grabowski, Wayne
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Malsawma, Lex H.
• Application Number:
  US10/767,028
• Publication Number:
  US 20040185622A1
• Time in Patent Office: 552 Days
• Field of Search: 438/212, 438/268, 438/270, 438/272, 438/430, 438/431
• US Class Current: 438/270
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-gated MOSFET formed using a super self aligned (SSA) process employs an insulating layer such as a glass layer and a contact mask to define contact openings for electrical connections to source regions of the MOSFET. Use a contact mask and an intervening glass in otherwise self-aligned process reduces the coupling capacitance between source metal and the top of the embedded trench gate. A metal layer deposited to make electrical contact to source regions can be planarized, for example, ground flat using chemical-mechanical polishing to provide a flat surface to avoid formation of conductive traces that extend over the steps that the glass layer forms.

Claims

1. A method for fabricating a MOSFET, comprising:

forming a hard mask on a surface of a semiconductor;

etching a trench in the semiconductor through an opening in the hard mask;

forming a first insulating layer inside the trench;

introducing a gate material into the trench, wherein the first insulating layer is between the gate material and the semiconductor;

forming a body region and a source region in the semiconductor adjacent to the trench;

oxidizing the gate material to form a second insulating layer overlying a remaining portion of the gate material, wherein the hard mask limits oxidation to areas that the hard mask exposes;

removing the hard mask;

depositing a third insulating layer;

etching an opening in the third insulating layer to expose the source region; and

depositing a contact material in the opening in the third insulating layer to thereby form a contact plug making electrical contact to the source region, wherein depositing the contact material comprises depositing a metal layer at a pressure of about two atmospheric pressures.

2. The method of claim 1, wherein the hard mask comprises a layer of silicon nitride.

3. The method of claim 1, wherein the gate material comprises polysilicon.

4. The method of claim 1, wherein depositing the third insulating layer comprises flowing a layer of glass over a surface of the second insulating layer and the semiconductor.

5. The method of claim 4, wherein the glass comprises borophosphosilicate glass.

6. The method of claim 1, further comprising forming a mask on the third insulating layer, wherein the mask on the third insulating layer has a pattern that controls a location of the opening in the third insulating layer.

7. The method of claim 1, wherein the metal layer comprises tungsten.

8. The method of claim 1, further comprising depositing a barrier layer on a surface of the semiconductor in the opening through the third insulating layer.

9. The method of claim 1, wherein removing the hard mask exposes the source region while the gate material remains protected by the second insulating layer.

10. A method of fabricating a MOSFET, comprising:

forming a trench in a surface of a semiconductor, the trench defining a mesa;

forming a first insulating layer along a wall of the trench;

forming a gate in the trench, the gate being insulated from the semiconductor by the first insulating layer;

forming a body region of a first conductivity type and a source region of a second conductivity type in the mesa;

forming a second insulating layer over the mesa;

etching an opening in the second insulating layer;

depositing a first metal layer that is in electrical contact with the source region through the opening in the second insulating layer wherein the depositing is performed at a pressure greater than atmospheric pressure;

planarizing the first metal layer to form a plug, a surface of the plug being coplanar with a surface of the second insulating layer; and

depositing a second metal layer over the second insulating layer and the plug.

11. The method of claim 10, wherein forming a second insulating layer comprises forming a glass layer.

12. The method of claim 10, wherein depositing a first metal layer comprises depositing a metal from the group consisting of tungsten and copper.

13. The method of claim 10, wherein planarizing the first metal layer comprises chemical-mechanical polishing.

14. The method of claim 10, wherein planarizing the first metal layer comprises etching.

15. The method of claim 10, wherein forming the trench comprises:

forming a hard mask having an opening overlying the semiconductor; and

etching the semiconductor through the opening in the hard mask to form the trench.

16. The method of claim 15, wherein forming a gate in the trench comprises depositing polysilicon into the trench.

17. The method of claim 16, further comprising oxidizing the polysilicon layer to form a top oxide layer overlying a remaining portion of the polysilicon layer.

18. The method of claim 17, further comprising removing the hard mask after oxidizing the polysilicon layer and before forming the second insulating layer.

19. The method of claim 18, wherein removing the hard mask exposes the source region while the polysilicon in the trench remains protected by the top oxide layer.