Semiconductor package
First Claim
Patent Images
1. A semiconductor package, comprising:
- a chip assembly including;
at least two chips, each having an under bump metallurgy, wherein each under bump metallurgy has an extended portion that is electrically connected to the extended portion of the other under bump metallurgy; and
at least one slicing path located between said at least two chips; and
a substrate including an upper surface and a lower surface, wherein said upper surface is flip-chip bonded with said chip assembly.
1 Assignment
0 Petitions
Accused Products
Abstract
The present invention discloses a semiconductor package, wherein several chips can be packed thereinto. The present invention uses under bump metallurgies or bonding wires to connect the associated circuits of at least two chips in serial or in parallel. At least one slicing path is located between the at least two chips and a substrate is provided with an upper surface and a lower surface in which the upper surface is flip-chip bonded with the at least two chips.
-
Citations
6 Claims
-
1. A semiconductor package, comprising:
-
a chip assembly including;
at least two chips, each having an under bump metallurgy, wherein each under bump metallurgy has an extended portion that is electrically connected to the extended portion of the other under bump metallurgy; and
at least one slicing path located between said at least two chips; and
a substrate including an upper surface and a lower surface, wherein said upper surface is flip-chip bonded with said chip assembly. - View Dependent Claims (2, 3, 4, 5, 6)
-
Specification