Compact SRAM cell with FinFET

• US 6,924,560 B2
• Filed: 08/08/2003
• Issued: 08/02/2005
• Est. Priority Date: 08/08/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Chang-Ta, Wang, Ping-Wei
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US10/637,322
• Publication Number:
  US 20050029556A1
• Time in Patent Office: 725 Days
• Field of Search: 257 66- 69, 257/351, 257/369, 257/377, 257/382, 257/385, 257/388, 257/393, 257/903, 257/390, 257/368, 257/381, 257/413, 257/904, 257/538, 365/154, 365/156, 365/180, 365/182
• US Class Current: 257/67
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

A method and system is disclosed for an SRAM device cell having at least one device of a first semiconductor type and at lease one device of a second semiconductor type. The cell has a first device of the first type constructed as a part of a first FinFET having one or more devices of the first type, a first device of the second type whose poly region is an extension of a poly region of the first device of the first type with no contact needed to connect therebetween, wherein the two devices are constructed using a silicon-on-insulator (SOI) technology so that they are separated by an insulator region therebetween so as to minimize the distance between the two devices.

Claims

1. An SRAM device cell having at least one device of a first semiconductor type and at lease one device of a second semiconductor type, comprising:

a first device of the first type constructed as a part of a first FinFET having one or more devices of the first type;

a first device of the second type whose poly region is an extension of a poly region of the first device of the first type with no contact needed to connect there between;

wherein an active region of the first device of the second type is connected to a poly region of a second device of the second type,

wherein the two devices are constructed using a silicon-on-insulator (SOI) technology so that they are separated by an insulator region there between so as to minimize the distance between the two devices.

2. The SRAM device cell of claim 1 wherein the first FinFET further includes a second P type device.

3. The SRAM device cell of claim 1 wherein the active region of the first device of the second type is connected by sharing a butted contact.

4. The SRAM device cell of claim 1 wherein the first device of the first type is a driver transistor.

5. The SRAM device cell of claim 1 wherein the first device of the second type is a load transistor.

6. The SRAM device cell of claim 1 wherein the two devices are connected in series.

7. The SRAM device cell of claim 1 wherein the distance between the two devices is a minimum required distance between two active regions according to a design rule for a predetermined generation of technology.

8. An SRAM device cell having at least one device of a first semiconductor type and at lease one device of a second semiconductor type, comprising:

a first device of the first type constructed as a part of a first FinFET having one or more devices of the first type;

a first device of the second type whose poly region is an extension of a poly region of the first device of the first type with no contact needed to serially connect there between,

wherein the two devices are constructed using a silicon-on-insulator (SOI) technology so that they are separated by an insulator region there between so as to minimize the distance between the two devices,

wherein the first device of the second type is connected to a positive power supply and the first device of the first type is connected to a negative power supply or ground.

9. An SRAM device cell having at least one device of a first semiconductor type and at least one device of a second semiconductor type, comprising:

a first device of the first type constructed as a part of a first FinFET having one or more devices of the first type; and

a first device of the second type constructed as a part of a second FinFET having one or more devices of the second type,

wherein an active region of the first device of the second type is connected to a poly region of a second device of the second type,

wherein the first and second devices share a poly region, and

wherein the two devices are constructed using a silicon-on-insulator (SOI) technology so that they are separated by an insulator region so as to minimize the distance between two active regions for the FinFETs.

10. The SRAM device cell of claim 9 wherein the distance between two active regions for the FinFETs is equal to or more than a minimum required distance between two active regions according to a design rule of a predetermined generation of technology.

11. The SRAM device cell of claim 9 wherein the second FinFET further includes a second device of the first type.

12. The SRAM device cell of claim 9 wherein the first device of the first type is a load transistor.

13. The SRAM device cell of claim 9 wherein the first device of the second type is a driver transistor.

14. The SRAM device cell of claim 9 wherein the second device of the first type is a transfer transistor.

15. An SRAM device cell having at least one device of a first semiconductor type and at lease one device of a second semiconductor type, comprising:

a first device of the first type constructed as a part of a first FinFET having one or more devices of the first type; and

a first device of the second type constructed as a part of a second FinFET having one or more devices of the second type,

wherein the first and second devices share a poly region,

wherein the two devices are constructed using a silicon-on-insulator (SOI) technology so that they are separated by an insulator region so as to minimize the distance between two active regions for the FinFETs,

wherein the first device of the first type is connected to a positive power supply and the first device of the second type is connected to a negative power supply or ground.

16. An SRAM device cell comprising:

a first FinFET having a first and second load devices of a first type; and

a second FinFET having a first and second driver devices of a second type,

wherein an active region of the first device of the second type is connected to a poly region of a second device of the second type,

wherein the first load device and the first driver device share a first poly region,

wherein the second load device and the second driver device share a second poly region, and

wherein the two FinFETs are constructed using a silicon-on-insulator (SOI) technology so that active regions thereof are separated by an insulator region so as to minimize the distance therebetween.

17. The SRAM device cell of claim 16 wherein the distance between the two active regions for the FinFETs is equal to or more than a minimum required distance between two active regions according to a design rule of a predetermined generation of technology.

18. The SRAM device cell of claim 16 wherein the active region of the first FinFET between the two poly regions is connected to Vcc.

19. The SRAM device cell of claim 16 wherein the active region of the second FinFET between the two poly regions is connected to Vss.

20. An SRAM device cell comprising:

a first FinFET having a first and second load devices of a first type; and

a second FinFET having a first and second driver devices of a second type,

wherein the first load device and the first driver device share a first poly region,

wherein the second load device and the second driver device share a second poly region,

wherein the two FinFETs are constructed using a silicon-on-insulator (SOI) technology so that active regions thereof are separated by an insulator region so as to minimize the distance therebetween,

wherein the second FinFET further includes two transfer transistors of the second type.