Level shifting and level-shifting amplifier circuits

• US 6,924,667 B2
• Filed: 07/19/2002
• Issued: 08/02/2005
• Est. Priority Date: 07/19/2002
• Status: Expired due to Fees

• Current Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Original Assignee: O2 Micro International Limited (O2 Micro Incorporated)
• Inventors: Li, Guoxing, Liu, Liusheng
• Primary Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US10/200,006
• Publication Number:
  US 20040012410A1
• Time in Patent Office: 1,110 Days
• Field of Search: 326 63- 64, 326/68, 326/80, 326/33, 326 86- 87, 327 74- 75, 327/77, 327108-109, 327/80
• US Class Current: 326/80
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

Level shifting and amplified level shifting circuit topologies are provided that include two or more level shifting or amplified level shifting circuits. The level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted with respect to the input signals. The amplified level shifting circuits receive a variable and fixed input and generate a variable and fixed output that are level shifted and amplified with respect to the input signals. These circuits may be utilized to form a detection circuit that detects a difference in the output signals.

Claims

1. A level shifting circuit topology, comprising first, second, and third level shifting circuits, said first level shifting circuit generating a level shifted output signal from a variable input signal, said second level shifting circuit generating a fixed level shifted output threshold signal from a fixed input reference signal, and said third level shifting circuit generating a second fixed level shifted output threshold signal from said fixed input reference signal;

said first, second and third level shifting circuits being biased with respect to each other so that each has a DC transfer curve that is shifted with respect to the other.

2. The level shifting circuit as claimed in claim 1, said second level shifting circuit being biased so that its DC transfer curve is shifted between the shifted DC transfer curves of said first and third level shifting circuits.

3. The level shifting circuit topology as claimed in claim 1, wherein said first, second and third level shifting circuits each comprise:

a load transistor coupled to a first voltage source;

a source follower transistor coupled to a second voltage source, and

a bias resistor coupled between said load transistor and said source follower.

4. The level shifting circuit topology as claimed in claim 3, further comprising a bias circuit generating a bias voltage for biasing said load transistor, said fixed input signal or said variable input signal controlling the conduction state of said source follower transistor.

5. The level shifting circuit topology as claimed in claim 3, wherein a first bias resistor associated with said first level shifting circuit has a value less than a second bias resistor associated with said second level shifting circuit, which has a value less than a third bias resistor associated with said third level shifting circuit.

6. The level shifting circuit topology as claimed in claim 1, wherein said DC transfer curves are right shifted with respect to a supply voltage.

7. The level shifting circuit topology as claimed in claim 1, wherein said DC transfer curves are left shifted with respect to a supply voltage.

8. The level shifting circuit topology as claimed in claim 1, wherein said DC transfer curves are shifted to be approximately in the middle of two supply voltages.

9. An amplifying level shifting circuit topology comprising first and second amplifying level shifting circuits, said first amplifying level shifting circuit generating an amplified and level shifted output signal from a variable input signal, and said second amplifying level shifting circuit generating a fixed, amplified and level shifted output threshold signal from a fixed input reference signal, said first and second amplifying level shifting circuits being biased with respect to each other so that each has a DC transfer curve that is shifted with respect to the other;

said amplifying level shifting circuit topology further comprising a third amplifying level shifting circuit generating a second fixed, amplified level shifted output threshold signal from said fixed input reference signal, said first, second and third amplifying level shifting circuits being biased with respect to each other so that each has a DC transfer curve that is shifted with respect to the other.

10. The amplifying level shifting circuit as claimed in claim 9, wherein said second amplifying level shifting circuit being biased so that its DC transfer curve is shifted between the shifted DC transfer curves of said first and third amplifying level shifting circuits.

11. The amplifying level shifting circuit topology as claimed in claim 9, wherein said first, second and third level shifting circuits each comprise:

a first branch circuit for level shifting said input signal, said first branch further comprising a load resistor for determining the shift of said input signal, and;

a second branch for amplifying said input signal.

12. The amplifying level shifting circuit topology as claimed in claim 11, further comprising a bias circuit generating a bias voltage for biasing said first branch.

13. The amplifying level shifting circuit topology as claimed in claim 11, wherein a first load resistor associated with said first amplifying level shifting circuit has a value less than a second load resistor associated with a second amplifying level shifting circuit, which has a value less than a third load resistor associated with a third amplifying level shifting circuit.

14. A level shifting circuit topology, comprising first, second and third level shifting circuits, said second level shifting circuit generating a level shifted output signal from a variable input signal, and said first and third level shifting circuits generating fixed, level shifted output threshold signals from a fixed input reference signal;

said level shifting circuits being biased with respect to each other so that each has a DC transfer curve that is shifted with respect to the other.

15. The level shifting circuit as claimed in claim 14, said second level shifting circuit being biased so that its DC transfer curve is shifted between the shifted DC transfer curves of said first and third level shifting circuits.

16. An amplified level shifting circuit topology, comprising first, second and third amplifying level shifting circuits wherein said second amplifying level shifting circuit generates an amplified and level shifted output signal from a variable input signal, and said first and third amplifying level shifting circuit generate fixed, amplified and level shifted output threshold signals from a fixed input reference signal;

said amplifying level shifting circuits being biased with respect to each other so that each has a DC transfer curve that is shifted with respect to the other.

17. The amplified level shifting circuit as claimed in claim 16, said second amplifying level shifting circuit being biased so that its DC transfer curve is shifted between the shifted DC transfer curves of said first and third amplifying level shifting circuits.

18. A detection circuit, comprising:

first, second and third level shifting circuits, said first level shifting circuit generating a level shifted output signal from a variable input signal, said second level shifting circuit generating a fixed level shifted output threshold signal from a fixed input reference signal, and said third level shifting circuit generating a second fixed level shifted output signal;

a first comparator receiving said level shifted output signal and said fixed level shifted output signal and generating a signal indicative of the difference between said level shifted output signal and said fixed level shifted output signal; and

a second comparator receiving said level shifted output signal and said second fixed level shifted output signal and generating a second signal indicative of the difference between said level shifted output signal and said second fixed level shifted output signal.

19. The detection circuit as claimed in claim 18, further comprising a logic gate receiving said first and second signals and generating a detection signal having a state defined by said first or second signal.

20. The detection circuit as claimed in claim 19, said logic gate comprising an XOR gate.

21. The detection circuit as claimed in claim 18, said level shifting circuits being biased with respect to each other so that each has a DC transfer curve that is shifted with respect to the other.

22. The detection circuit, as claimed in claim 18, said level shifting circuits being biased with respect to each other so that each has a DC transfer curve that is shifted with respect to the other.

23. The detection circuit as claimed in claim 22, said second level shifting circuit being biased so that its DC transfer curve is shifted between the shifted DC transfer curves of said first and third level shifting circuits.

24. A detection circuit comprising:

first and second amplifying level shifting circuits, said first amplifying level shifting circuit generating an amplified and level shifted output signal from a variable input signal, and said second amplifying level shifting circuit generating a fixed, amplified, and level shifted output threshold signal from a fixed input reference signal;

a comparator receiving said amplified and level shifted output signal and said fixed, amplified and level shifted output signal and generating a signal indicative of the difference between said amplified and level shifted output signal and said fixed, amplified, and level shifted output signal;

a third amplifying level shifting circuit generating a second fixed, amplified level shifted output signal; and

a second comparator receiving said amplified and level shifted output signal and said second fixed, amplified and level shifted output signal and generating a second signal indicative of the difference between said amplified and level shifted output signal and said second fixed, amplified and level shifted output signal.

25. The detection circuit as claimed in claim 24, further comprising a logic gate receiving said first and second signals and generating a detection signal having a state defined by said first or second signal.

26. The detection circuit as claimed in claim 25, wherein said logic gate comprises an XOR gate.

27. The detection circuit as claimed in claim 24, said amplifying level shifting circuits being biased with respect to each other so that each has a DC transfer curve that is shifted with respect to the other.

28. The detection circuit as claimed in claim 27, said second amplifying level shifting circuit being biased so that its DC transfer curve is shifted between the shifted DC transfer curves of said first and third amplifying level shifting circuits.