Ferroelectric memory and method of operating same
First Claim
1. A ferroelectric memory comprising a memory cell, and a circuit for reading and writing to said memory cell, wherein said circuit for reading and writing includes a drive line on which voltages for writing information to said memory cell and for reading information from said memory cell are placed, a bit line on which information to be read out of said memory cell is placed, a preamplifier having a preamplifier output providing a preamplifier output signal, said preamplifier connected between said memory cell and said bit line with said preamplifier output signal being applied to said bit line, a set switch connected between said drive line and said memory cell, and a reset switch connected to said memory cell.
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Accused Products
Abstract
A ferroelectric memory 636 includes a group of memory cells (645, 12, 201, 301, 401, 501), each cell having a ferroelectric memory element (44, 218, etc.), a drive line (122, 322, 422, 522 etc.) on which a voltage for writing information to the group of memory cells is placed, a bit line (25, 49, 125, 325, 425, 525, etc.) on which information to be read out of the group of memory cells is placed, a preamplifier (20, 42, 120, 320, 420, etc.) between the memory cells and the bit line, a set switch (14, 114, 314, 414, 514, etc.) connected between the drive line and the memory cells, and a reset switch (16, 116, 316, 416, 516, etc.) connected to the memory cells in parallel with the preamplifier. The memory is read by placing a voltage less than the coercive voltage of the ferroelectric memory element across a memory element. Prior to reading, noise from the group of cells is discharged by grounding both electrodes of the ferroelectric memory element.
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Citations
12 Claims
- 1. A ferroelectric memory comprising a memory cell, and a circuit for reading and writing to said memory cell, wherein said circuit for reading and writing includes a drive line on which voltages for writing information to said memory cell and for reading information from said memory cell are placed, a bit line on which information to be read out of said memory cell is placed, a preamplifier having a preamplifier output providing a preamplifier output signal, said preamplifier connected between said memory cell and said bit line with said preamplifier output signal being applied to said bit line, a set switch connected between said drive line and said memory cell, and a reset switch connected to said memory cell.
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6. A ferroelectric memory as in claim wherein said reset switch is connected in parallel with said preamplifier between said memory cell and said bit line.
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7. A ferroelectric memory comprising a plurality of memory cells and a circuit for reading and writing to said memory cells, wherein each of said memory cells comprise a memory cell transistor and a ferroelectric capacitor said memory cell transistor and ferroelectric capacitor connected in parallel, and wherein said circuit for reading and writing includes:
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a plurality of read transistors, each of said read transistors including a gate, said gate connected to one of said memory cells;
a source of a reset signal; and
a plurality of reset switches, each of said reset switches connected between said source of a reset signal and said gate of said read transistor. - View Dependent Claims (8)
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9. A ferroelectric memory comprising a plurality of memory cells and a circuit for reading and writing to said memory cells, wherein each of said memory cells comprise a memory cell transistor and a ferroelectric capacitor said memory cell transistor and ferroelectric capacitor connected in parallel, and wherein said circuit for reading and writing includes:
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a source of a set signal; and
a plurality of set switches, each of said set switches connected in series between said one of said memory cells and said source of a set signal. - View Dependent Claims (10)
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Specification
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- Resources
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Current AssigneePanasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
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Original AssigneeMatsushita Electric Industrial Company Limited (Panasonic Holdings Corporation), Symetrix Corporation
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InventorsLim, Myoungho, Paz de Araujo, Carlos A., Chen, Zheng, Kato, Yoshihisa, Shimada, Yasuhiro, Joshi, Vikram, McMillan, Larry D., Otsuki, Tatsuo
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Primary Examiner(s)LE, THONG QUOC
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Application NumberUS10/381,235Publication NumberTime in Patent Office1,407 DaysField of Search365/145, 365/189.01, 365/117US Class Current365/145CPC Class CodesG11C 11/22 using ferroelectric elements
