Semiconductor device

• US 6,925,006 B2
• Filed: 11/28/2003
• Issued: 08/02/2005
• Est. Priority Date: 06/18/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Innovative Silicon, S.A.
• Inventors: Fazan, Pierre, Okhonin, Serguei
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): LOUIE, WAI SING
• Application Number:
  US10/724,377
• Publication Number:
  US 20040135202A1
• Time in Patent Office: 613 Days
• Field of Search: 438128-132, 438197-199, 438/292, 438/587, 438/982, 365/185, 365/189
• US Class Current: 365/185.14
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench
• CPC Class Codes: Y10S 257/907 Folded bit line dram configuration
• CPC Class Codes: Y10S 438/982 Varying orientation of devices in array

Abstract

A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

Claims

1. A semiconductor memory array comprising:

a plurality of memory cells arranged in a matrix of rows and columns, the plurality of memory cells include a first memory cell and a second memory cell, wherein the first and second memory cells each include at least a transistor to constitute the memory cell and wherein the transistor includes;

a source region;

a drain region;

a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and

a gate disposed over the body region; and

wherein each memory cell includes;

a first data state representative of a first charge in the body region; and

a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and

wherein the source region of the transistor of the first memory cell and the source region of the transistor of the second memory cell are the same region.

2. The memory array of claim 1, further including a control unit, coupled to the gate and the drain region of the transistor of the first memory cell, to provide control signals to the transistor of the first memory cell, wherein the transistor of the first memory cell, in response to first write control signals, stores the first charge in the body region.

3. The memory array of claim 2 wherein the first charge is comprised of an accumulation of majority carriers in the body region.

4. The memory array of claim 3 wherein the majority carriers accumulate in a portion of the body region that is adjacent to the source region.

5. The memory array of claim 1 further including a control unit, coupled to the gate and the drain region of the transistor of the first memory cell, to provide control signals to the transistor of the first memory cell, wherein the transistor of the first memory cell, in response to second write control signals, stores the second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region.

6. The memory array of claim 5 wherein the second write control signals include at least first and second signals, each having positive voltages, wherein the first signal is applied to the drain region of the transistor of the first memory cell and the second signal is applied to the gate of the transistor of the first memory cell.

7. The memory array of claim 1 further including:

a reading unit, coupled to the drain region of the transistor of the first memory cell, to determine the data state of the transistor of the first memory cell;

a control unit, coupled to gate of the transistor of the first memory cell, to provide control signals to the transistor of the first memory cell; and

wherein, in response to a read control signal applied to the gate of the transistor of the first memory cell, the reading unit determines the charge stored in the body region of the transistor of the first memory cell.

8. The memory array of claim 1 wherein the source regions of the transistors of the first and second memory cells are connected to a fixed voltage.

9. A semiconductor memory array comprising:

a plurality of memory cells arranged in a matrix of rows and columns, the plurality of memory cell include a first memory cell and a second memory cell, wherein the first and second memory cells each include at least a transistor to constitute the memory cell wherein the transistor includes;

a source region having impurities to provide a first conductivity type;

a drain region having impurities to provide the first conductivity type;

a body region disposed between the source region and the drain region wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different than the first conductivity type;

a gate disposed over the body region; and

wherein each memory cell includes;

a first data state representative of a first charge in the body region wherein the first charge is substantially provided by impact ionization; and

a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and

wherein the source region of the transistor of the first memory cell and the source region of the transistor of the second memory cell are the same region.

10. The memory array of claim 9 further including a control unit, coupled to the gate and drain region of the transistor of the first memory cell, to apply control signals to the transistor of the first memory cell wherein the control signals include first write control signals to accumulate the first charge in the body of the transistor of the first memory cell and second write control signals to provide the second charge in the body region by removing charge from the body region through the source region.

11. The memory array of claim 10 wherein the first charge is stored in the body region of the transistor of the first memory cell in response to applying a first signal, having a first negative voltage, to the drain region and a second signal, having a second negative voltage, to the gate.

12. The memory array of claim 11 wherein the transistor of the first memory cell stores at least a substantial portion of the first charge in a portion of the body region of the transistor of the first memory cell that is adjacent to the source region of the transistor of the first memory cell.

13. The memory array of claim 10 wherein the second write control signals include a first signal, having a first positive voltage, applied to the drain region of the transistor of the first memory cell and a second signal, having a second positive voltage, applied to the gate of the transistor of the first memory cell.

14. The memory array of claim 13 wherein the source regions of the transistor of the first and second memory cells are connected to a fixed voltage.

15. The memory array of claim 14 wherein the second charge is stored in the body region in response to removing the first positive voltage from the drain region of the transistor of the first memory cell before removing the second positive voltage from the gate of the transistor of the first memory cell.

16. The memory array of claim 15 wherein, in response to the first and second positive voltages, the transistor of the first memory cell includes a forward bias current between its body region and its source region.

17. The memory array of claim 16 wherein the second charge is stored in the body region of the transistor of the first memory cell in response to removing the first positive voltage from the drain region of the transistor of the first memory cell and the second positive voltage from the gate of the transistor of the first memory cell.

18. The memory array of claim 9 including:

a reading unit, coupled to the drain region of the transistor of the first memory cell, to determine the data state of the transistor of the first memory cell;

a control unit, coupled to gate of the transistor of the first memory cell, to provide control signals to the transistor of the first memory cell; and

wherein, in response to a read control signal applied to the gate of the transistor of the first memory cell, the reading unit determines the charge stored in the body region of the transistor of the first memory cell.

19. The memory array of claim 10 wherein the second write control signal include a first signal, having a first positive voltage, applied to the drain region of the transistor of the first memory cell.

20. The memory array of claim 19 wherein the second charge is stored in the body region in response to removing the first positive voltage from the drain region of the transistor of the first memory cell before removing the second positive voltage from the gate of the transistor of the first memory cell.

21. The memory array of claim 20 wherein, in response to the first and second positive voltages, the transistor of the first memory cell includes a forward bias current between its body region and its source region.

22. The memory array of claim 21 wherein the second charge is stored in the body region of the transistor of the first memory cell in response to removing the first positive voltage from the drain region of the transistor of the first memory cell and wherein the source regions of the transistors of the first and second memory cells are connected to a fixed voltage.

23. A semiconductor memory array comprising:

a plurality of memory cells, arranged in a matrix of rows and columns, including a first memory cell and a second memory cell, wherein the first and second memory cells each include at least a transistor to constitute the memory cell wherein the transistor includes;

a source region having impurities to provide a first conductivity type;

a drain region having impurities to provide the first conductivity type;

a body region disposed between the source region and the drain region wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different than the first conductivity type;

a gate spaced apart from, and capacitively coupled to, the body region; and

wherein each memory cell includes;

a first data state representative of a first charge in the body; and

a second data state representative of a second charge in the body region wherein the second charge is substantially provided by removing charge from the body region through the source region; and

wherein the source region of the transistor of the first memory cell and the source region of the transistor of the second memory cell are the same source region.

24. The memory array of claim 23 further including a control unit, coupled to the transistor of the first memory cell, to control the data state of the transistor of the first memory cell wherein, in response to a first voltage applied to the drain region of the transistor of the first memory cell and a second voltage applied to the gate of the transistor of the first memory cell, the first charge is removed from the body region of the transistor of the first memory cell through its source region.

25. The memory array of claim 24 wherein the control unit, in response to removing the first voltage from the drain region of the transistor of the first memory cell before removing the second voltage from the gate of the transistor of the first memory cell, causes the second charge to be stored in the body region of the transistor of the first memory cell.

26. The memory array of claim 24 wherein the control unit, in response to applying ground to the drain region of the transistor of the first memory cell before removing the second voltage from the gate of the transistor of the first memory cell, causes the second charge to be stored in the body region of the transistor of the first memory cell.

27. The memory array of claim 24 wherein the control unit, in response to applying a third voltage to the drain region of the transistor of the first memory cell before applying a fourth voltage to the gate of the transistor of the first memory cell, causes the transistor of the first memory cell to store the second charge in its body region.

28. The memory array of claim 24 wherein the transistor of the first memory cell stores the first charge in a portion of its body region that is adjacent to its source region.

29. The memory array of claim 24 further including a control unit, coupled to the gate and the drain region of the transistor of the first memory cell, to apply control signals to transistor of the first memory cell wherein:

in response to first write control signals, the transistor of the first memory cell generates and stores the first charge in the body region; and

in response to second write control signals, the transistor of the first memory cell generates and stores the second charge in the body region wherein the transistor of the first memory cell generates the second charge by removing charge from its body region through its source region; and

wherein the first and second write control signals each include a plurality of signals.

30. The memory array of claim 29 wherein the first write control signals include a first signal having a first negative voltage to the drain and a second signal having a second negative voltage to the gate and wherein, in response to the first and second negative voltages, the first charge is stored in the body region of the transistor of the first memory cell.

31. The memory array of claim 30 wherein the transistor of the first memory cell stores the first charge in a portion of the body region of the transistor of the first memory cell that is adjacent to the source region of the transistor of the first memory cell.

32. The memory array of claim 29 wherein the second write control signals include a first signal having a first positive voltage applied to the drain region and a second signal having a second positive voltage applied to the gate.

33. The memory array of claim 32 wherein the second charge is stored in the body region in response to removing the first positive voltage from the drain region of the transistor of the first memory cell before removing the second positive voltage from the gate of the transistor of the first memory cell.

34. The memory array of claim 32 wherein, in response to the first and second positive voltages, the transistor of the first memory cell includes a forward bias current between its body region and the source region.

35. The memory array of claim 34 wherein the second charge is stored in the body region of the transistor of the first memory cell in response to removing the first positive voltage from the drain region of the transistor of the first memory cell and the second positive voltage from the gate of the transistor of the first memory cell.

36. The memory array of claim 23 further including:

a reading unit, coupled to the drain region of the transistor of the first memory cell, to determine the data state of the transistor of the first memory cell;

a control unit, coupled to gate of the transistor of the first memory cell, to provide control signals to the transistor of the first memory cell; and

wherein, in response to a read control signal applied to the gate of the transistor of the first memory cell, the reading unit determines the charge stored in the body region of the transistor of the first memory cell.