Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs

• US 6,925,021 B2
• Filed: 01/10/2002
• Issued: 08/02/2005
• Est. Priority Date: 03/08/2001
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Shore, Michael A., Mullarkey, Patrick J., Cowles, Timoty B.
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US10/043,680
• Publication Number:
  US 20020126558A1
• Time in Patent Office: 1,300 Days
• Field of Search: 365/222, 365/149, 365/230.04, 365/230.06, 365/233
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the half density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode. The SDRAM also includes circuitry for remapping one of the row address bits for use as a column address bit in the half density mode so that the SDRAM can interface with system adapted for conventional dual mode SDRAMs.

Claims

1. A refresh controller for use in a dynamic random access memory (“

DRAM”

) having a full density mode and a reduced density mode, the refresh controller comprising;

an oscillator generating a periodic clock signal;

a counter having a clock input terminal coupled to receive the clock signal, the counter having first and second stages the first of which increments at a faster rate than the second, the second stage of the being two stages from the first stage of the counter so that the second stage is incremented at one-quarter the rate of the first stage; and

a selector circuit coupled the first and second stages of the counter, the selector circuit being operable to couple the first stage of the counter to an output terminal in the full density mode and being operable to couple the second stage of the counter to the output terminal in the reduced density mode.

2. The refresh controller of claim 1 wherein the selector circuit comprises:

a first pass gate coupled between the first stage of the counter and the output terminal;

a second pass gate coupled between the second stage of the counter and the output terminal; and

a control circuit for enabling the first pass gate and disabling the second pass gate in the full density mode and for disabling the first pass gate and enabling the second pass gate in the reduced density mode.

3. The refresh controller of claim 1 wherein the reduced density mode comprises a half density mode.

4. A dynamic random access memory (“

DRAM”

) comprising;

an array of memory cells arranged in rows and columns;

a column address latch structured to store a colunm address responsive to a column address strobe signal;

a column decoder coupled to the column address latch to receive the stored column address and enable respective sense amplifiers corresponding thereto;

a row address latch structured to store a row address responsive to a row address strobe signal;

a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;

a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;

a mode controller coupled to the row decoders, the mode controller being operable in a full density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in a reduced density mode regardless of the state of the least significant bit of the row address;

a data path coupled between the memory array and a data terminal; and

a refresh controller for refreshing at least some of the memory cells in the memory array responsive to a refresh trigger signal, the refresh controller comprising;

an oscillator generating a periodic clock signal;

a counter having a clock input terminal coupled to receive the clock signal, the counter having first and second stages the first of which increments at a faster rate than the second, the second stage of the counter being two stages from the first stage of the counter so that the second stage is incremented at one-quarter the rate of the first stage; and

a selector circuit coupled the first and second stages of the counter, the selector circuit being operable to couple the first stage of the counter to an output terminal in the full density mode and being operable to couple the second stage of the counter to the output terminal in the reduced density mode, the refresh trigger signal being generated responsive to the counter stage coupled to the output terminal by the selector circuit being incremented or decremented.

5. The dynamic random access memory of claim 4 wherein the selector circuit comprises:

a first pass gate coupled between the first stage of the counter and the output terminal;

a second pass gate coupled between the second stage of the counter and the output terminal; and

a control circuit for enabling the first pass gate and disabling the second pass gate in the full density mode and for disabling the first pass gate and enabling the second pass gate in the reduced density mode.

6. A computer system, comprising:

a data input device;

a data output device;

a processor coupled to the data input and output devices; and

a dynamic random access memory, comprising;

an array of memory cells arranged in rows and columns;

a column address latch structured to store a column address responsive to a column address strobe signal;

a column decoder coupled to the column address latch to receive the stored column address and enable respective sense amplifiers corresponding thereto;

a row address latch structured to store a row address responsive to a row address strobe signal;

a first row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the first row decoder being enable responsive to a first enable signal;

a second row decoder coupled to the row address latch to receive the stored row address and activate respective word lines corresponding thereto, the row lines activated by the first row decoder being interleaved with the row lines activated by the second row decoder, the second row decoder being enabled responsive to a second enable signal;

a mode controller coupled to the row decoders, the mode controller being operable in the full density mode to generate the first enable signal responsive to a first state of a least significant bit of the row address and to generate the second enable signal responsive to a second state of the least significant bit of the row address, the mode controller further being operable to generate the first and second enable signals in a reduced density mode regardless of the state of the least significant bit of the row address;

a data path coupled between the memory array and a data terminal; and

a refresh controller for refreshing at least some of the memory cells in the memory array responsive to a refresh trigger signal, the refresh controller comprising;

an oscillator generating a periodic clock signal;

a counter having a clock input terminal coupled to receive the clock signal, the counter having first and second stages the first of which increments at a faster rate than the second, the second stage of the counter being two stages from the first stage of the counter so that the second stage is incremented at one-quarter the rate of the first stage; and

a selector circuit coupled the first and second stages of the counter, the selector circuit being operable to couple the first stage of the counter to an output terminal in the full density mode and being operable to couple the second stage of the counter to the output terminal in the reduced density mode, the refresh trigger signal being generated responsive to the counter stage coupled to the output terminal by the selector circuit being incremented or decremented.

7. The computer system of claim 6 wherein the selector circuit comprises:

a first pass gate coupled between the first stage of the counter and the output terminal;

a second pass gate coupled between the second stage of the counter and the output terminal; and

a control circuit for enabling the first pass gate and disabling the second pass gate in the full density mode and for disabling the first pass gate and enabling the second pass gate in the reduced density mode.