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Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs

  • US 6,925,021 B2
  • Filed: 01/10/2002
  • Issued: 08/02/2005
  • Est. Priority Date: 03/08/2001
  • Status: Expired due to Fees
First Claim
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1. A refresh controller for use in a dynamic random access memory (“

  • DRAM”

    ) having a full density mode and a reduced density mode, the refresh controller comprising;

    an oscillator generating a periodic clock signal;

    a counter having a clock input terminal coupled to receive the clock signal, the counter having first and second stages the first of which increments at a faster rate than the second, the second stage of the being two stages from the first stage of the counter so that the second stage is incremented at one-quarter the rate of the first stage; and

    a selector circuit coupled the first and second stages of the counter, the selector circuit being operable to couple the first stage of the counter to an output terminal in the full density mode and being operable to couple the second stage of the counter to the output terminal in the reduced density mode.

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