Zero power chip standby mode

• US 6,925,024 B2
• Filed: 08/28/2002
• Issued: 08/02/2005
• Est. Priority Date: 08/30/2001
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Lovett, Simon J., Pawlowski, J. Thomas, Higgins, Brian P.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US10/232,935
• Publication Number:
  US 20030058704A1
• Time in Patent Office: 1,070 Days
• Field of Search: 365/226, 365/229, 365/63
• US Class Current: 365/226
• CPC Class Codes: G11C 5/141 Battery and back-up supplies

Abstract

A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.

Claims

1. A method of implementing a standby mode in a system comprising the acts of:

delivering a control signal to the input of an isolation circuit internal to a memory device, the isolation circuit being coupled between a power supply and an internal power bus that is internal to the memory device, wherein the control signal is delivered in response to a power down state;

providing a power signal to the isolation circuit and to one or more components, wherein the one or more components are not coupled directly to the internal power bus;

providing the power signal to an input buffer and circuitry regardless of the power down state, wherein the input buffer and circuitry are internal to the memory device and coupled to the isolation circuit; and

isolating the power supply from the internal power bus by interrupting the path between the power supply and the internal power bus, wherein the isolation circuit is configured to disconnect the power signal from the internal power bus in response to the occurrence of an event without disconnecting the power signal from the one or more components.

2. The method of implementing a standby mode in a system, as set forth in claim 1, wherein the act of delivering the control signal to the isolation circuit comprises the act of delivering the control signal to a p-channel field effect transistor (FET).

3. The method of implementing a standby mode in a system, as set forth in claim 1, wherein the one or more components comprise an output buffer.

4. The method of implementing a standby mode in a system, as set forth in claim 1, wherein the event comprises the expiration of a counter.

5. A method of implementing a standby mode comprising the acts of:

receiving one of a first control signal and a second control signal at the input of an isolation circuit internal to a memory device;

providing a power signal to the isolation circuit and to one or more components, wherein the one or more components are not coupled directly to the internal power bus;

providing the power signal to an input buffer and circuitry regardless of the receipt of the first control signal or the second control signal by the isolation circuit, wherein the input buffer and circuitry are internal to the memory device and coupled to the isolation circuit;

coupling an external power supply to an internal power bus if the first control signal is received at the input of the isolation circuit; and

isolating the external power supply from the internal power bus by interrupting the path between the external power supply and the internal power supply bus if the second control signal is received at the input of the isolation circuit, wherein the isolation circuit is configured to disconnect the power signal from the internal power bus without disconnecting the power signal from the one or more components.

6. The method of implementing a standby mode, as set forth in claim 5, wherein the memory device comprises a Static Random Access Memory device.

7. The method of implementing a standby mode, as set forth in claim 5, wherein the external power supply comprises a power supply that is external to the memory device.

8. The method of implementing a standby mode, as set forth in claim 7, wherein the external power supply comprises a power supply of a computer system.

9. The method of implementing a standby mode, as set forth in claim 5, wherein isolating comprises isolating the external power supply from the internal power bus by interrupting the path between the external power supply and the internal power bus if a power down control signal is received at the input of the isolation circuit.

10. A method of implementing a standby mode for a memory device comprising the acts of:

delivering a control signal to a gate of an isolation transistor;

coupling a source and drain of the isolation transistor in series between an external power supply and an internal power bus internal to the memory device;

providing a power signal to the isolation transistor, an input buffer, circuitry and one or more components, wherein the input buffer, circuitry, and the one or more components are not coupled directly to the internal power bus; and

isolating the external power supply from the internal power bus by interrupting the path between the external power supply and the internal power bus, wherein the isolation transistor is configured to disconnect the power signal from the internal power bus in response to the occurrence of an event without disconnecting the power signal from the input buffer, circuitry, and the one or more components.

11. The method of implementing a standby mode for a memory device, as set forth in claim 10, wherein the isolation transistor comprises a p-channel field effect transistor (FET).

12. The method of implementing a standby mode for a memory device, as set forth in claim 10, wherein the power supply provides power to the memory device and a processor.

13. The method of implementing a standby mode for a memory device, as set forth in claim 10, wherein the control signal is correlative to a power down mode.

14. The method of implementing a standby mode for a memory device, as set forth in claim 10, wherein the control signal is correlative to a standby mode.

15. The method of implementing a standby mode for a memory device, as set forth in claim 10, wherein the control signal is correlative to a sleep state.