Controller with interface attachment

• US 6,925,407 B2
• Filed: 01/06/2004
• Issued: 08/02/2005
• Est. Priority Date: 07/12/1999
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Duppong, Charles M.
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): Miller, Craig Steven
• Application Number:
  US10/751,651
• Publication Number:
  US 20040209531A1
• Time in Patent Office: 574 Days
• Field of Search: 702117-120, 702121-123, 710/8, 713/1, 713/100
• US Class Current: 702/119
• CPC Class Codes: G05B 2219/23417 Read program from pluggable memory card
• CPC Class Codes: G05B 2219/25265 Flash memory
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

A controller with attachments for controlling specific electronic circuits is disclosed. Each attachment has a connector connectable to the electronic circuit to be controlled, and a memory accessible by the controller that contains configuration data for accessing the electronic circuit, and operational software for operating the electronic circuit.

Claims

1. A test system for testing an electronic circuit, said test system comprising:

a controller for testing the electronic circuit, said controller having a first connector; and

an application attachment having a second connector connectable to said first connector and a third connector connectable to the electronic circuit, said application attachment including a memory storing configuration data and a test program, said controller using the test program stored in said memory to test the electronic circuit.

2. The test system of claim 1, wherein the electronic circuit is an integrated circuit memory device.

3. The test system of claim 2, wherein the test program is a memory erase time test program.

4. The test system of claim 2, wherein the test program tests for failed memory locations in the integrated circuit memory device.

5. The test system of claim 1, wherein the electronic circuit is a memory circuit.

6. The test system of claim 5, wherein the test program is a memory erase time test program.

7. The test system of claim 5, wherein the test program tests for failed memory locations in the memory circuit.

8. The test system of claim 1, wherein said memory is a non-volatile memory device.

9. The test system of claim 1, wherein said memory is a flash memory device.

10. The test system of claim 1, wherein said application attachment further comprises a logic circuit connected between said second and third connectors.

11. A test system for testing an integrated circuit, said test system comprising:

a controller for testing the integrated circuit, said controller having a first connector; and

an application attachment having a second connector connectable to said first connector and an integrated circuit socket connectable to the integrated circuit, said application attachment including a memory storing configuration data and a test program, said controller using the test program stored in said memory to test the integrated circuit.

12. The test system of claim 11, wherein the integrated circuit is an integrated circuit memory device.

13. The test system of claim 12, wherein the test program is a memory erase time test program.

14. The test system of claim 12, wherein the test program tests for failed memory locations in the integrated circuit memory device.

15. The test system of claim 11, wherein said memory is a non-volatile memory device.

16. The test system of claim 11, wherein said memory is a flash memory device.

17. The test system of claim 11, wherein said application attachment further comprises a test circuit connected between said second connector and said integrated circuit socket.