Self-optimizing crossbar switch

• US 6,925,520 B2
• Filed: 05/31/2001
• Issued: 08/02/2005
• Est. Priority Date: 05/31/2001
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Ma, James H., Grenier, Lisa C.
• Primary Examiner(s): Rinehart, Mark H.
• Assistant Examiner(s): King, Justin
• Application Number:
  US09/871,277
• Publication Number:
  US 20040225787A1
• Time in Patent Office: 1,524 Days
• Field of Search: 315/189.01, 370/357, 370/360, 370/363, 710/5, 710/305, 710/311, 710/316, 710/317, 710/241, 710/244
• US Class Current: 710/317
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring
• CPC Class Codes: H04L 49/101 using crossbar or matrix

Abstract

A crossbar switch is disclosed. The crossbar switch comprises a plurality of input sorting units and a plurality of merge and interleave units. Each input sorting unit is capable of receiving from a respective device an access request to any one of a plurality of physical memory devices. Each merge and interleave unit is capable of arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests and forwarding the selected request for implementation on a respective memory device. Also disclosed is method implemented by the crossbar switch.

Claims

1. A crossbar switch, comprising:

a plurality of input sorting units, each input sorting unit capable of receiving from a respective device an access request to any one of a plurality of physical memory devices;

a plurality of merge and interleave units, each merge and interleave unit capable of arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests and forwarding the selected request for implementation on a respective memory device;

wherein each merge and interleave unit includes;

a priority generator for each input sorting unit capable of generating a composite request priority from a plurality of characteristics of the access requests and a plurality of operational characteristics;

a priority compare circuit capable of selecting one access request;

a request multiplexer controlled by the priority compare circuit to output the selected access request;

a plurality of programmable registers;

a decode unit receiving the selected request from the request multiplexer to determine whether the selected request is a register operation and, if so, to send a plurality of control and data signals to the registers; and

an output multiplexer for combining register read data with request data for output.

2. The crossbar switch of claim 1, further comprising a plurality of translation circuits and wherein each of the input sorting units receives the access requests through a respective one of the translation circuits.

3. The crossbar switch of claim 2, wherein each of the translation circuits is capable of receiving an opcode and a virtual address from their respective device, translating the opcode to determine whether the access request is a read or a write, and mapping the virtual address into a physical address, and forwarding the translated opcode and mapped physical address to its respective input sorting unit.

4. The crossbar switch of claim 1, wherein each of the input sorting units includes a buffer and is capable of buffering the access requests from its respective physical memory device.

5. The crossbar switch of claim 4, wherein the buffer is a first-in, first-out queue.

6. The crossbar switch of claim 4, wherein each of the input sorting units is capable of stalling its respective device when its buffer is full.

7. The crossbar switch of claim 1, wherein each merge and interleave unit further includes:

the priority generator for each input sorting unit being further capable of;

receiving the plurality of characteristics for the access request received by the input sorting unit;

receiving the plurality of operational characteristics; and

generating the composite request priority from the characteristics of the access requests and the operational characteristics;

the priority compare circuit being further capable of;

comparing the composite request priorities generated by the priority generators; and

selecting the one access request predicated on the comparison of the composite request priorities.

8. The crossbar switch of claim 1, further comprising:

a plurality of read buffers capable of receiving and buffering read data from a respective one of the physical memory devices; and

a plurality of output management units capable of receiving read data from the read buffers and forwarding the received read data to a respective one of the devices that generated the access request associated with the read data.

9. The crossbar switch of claim 1, further comprising a plurality of memory interfaces capable of receiving the selected access request from a respective one of the plurality of merge and interleave units and forwarding the selected access request to a respective one of the physical memory devices.

10. A crossbar switch, comprising a plurality of arbitration and select units, each arbitration and select unit including:

a plurality of front ends, each front end comprising;

a translation circuit capable of processing an access request received from a respective device;

an input sorting unit capable of buffering and forwarding the processed access request;

an output management unit capable of receiving read data generated by the access request and forwarding the received read data to the respective device; and

a plurality of back ends, each back end comprising;

a merge and interleave unit capable of arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests, and forwarding the selected request for implementation on a respective memory device;

wherein each merge and interleave unit includes;

a priority generator for each input sorting unit capable of generating a composite request priority from a plurality of characteristics of the access requests and a plurality of received operational characteristics;

a priority compare circuit capable of selecting one access request;

a request multiplexer controlled by the priority compare circuit to output the selected access request;

a plurality of programmable registers;

a decode unit receiving the selected request from the request multiplexer to determine whether the selected request is a register operation and, if so, to send a plurality of control and data signals to the registers; and

an output multiplexer for combining register read data with request data for output; and

a read buffer capable of receiving, buffering, and forwarding read data received from the respective memory device to the output management unit of the front end that issued a previously selected access request that generated the read data.

11. The crossbar switch of claim 10, wherein each back end further comprises a memory interface through which the merge and interleave unit forwards the selected request.

12. The crossbar switch of claim 10, wherein each of the translation circuits is capable of receiving an opcode and a virtual address from their respective device, translating the opcode to determine whether the access request is a read or a write, and mapping the virtual address into a physical address, and forwarding the translated opcode and mapped physical address to its respective input sorting unit.

13. The crossbar switch of claim 10, wherein each of the input sorting units includes a request buffer and is capable of buffering the access requests from its respective physical memory device.

14. The crossbar switch of claim 13, wherein the request buffer is a first-in, first-out queue.

15. The crossbar switch of claim 13, wherein each of the input sorting units is capable of stalling its respective device when its request buffer is full.

16. The crossbar switch of claim 10, wherein each merge and interleave unit further includes:

the priority generator for each input sorting unit being further capable of;

receiving the plurality of characteristics for the access request received by the input sorting unit;

receiving the plurality of operational characteristics; and

generating the composite request priority from the characteristics of the access requests and the operational characteristics;

the priority compare circuit being further capable of;

comparing the composite request priorities generated by the priority generators; and

selecting the one access request predicated on the comparison of the composite request priorities.

17. A crossbar switch, comprising a plurality of arbitration and select units, each arbitration and select unit including:

a plurality of front ends, each front end further including an input sorting unit capable of receiving from a respective device an access request to any one of a plurality of physical memory devices;

a plurality of back ends, each back end further including merge and interleave unit capable of arbitrating among competing access requests received from any of the input sorting units, selecting one of the competing access requests and forwarding the selected request for implementation on a respective memory device;

wherein each merge and interleave unit includes;

a priority generator for each input sorting unit capable of generating a composite request priority from a plurality of characteristics of the access requests and a plurality of received operational characteristics;

a priority compare circuit capable of selecting one access request;

a request multiplexer controlled by the priority compare circuit to output the selected access request;

a plurality of programmable registers;

a decode unit receiving the selected request from the request multiplexer to determine whether the selected request is a register operation and, if so, to send a plurality of control and data signals to the registers; and

an output multiplexer for combining register read data with request data for output.

18. The crossbar switch of claim 17, wherein each front end further comprises a Glue logic unit and wherein each of the input sorting units receives the access requests through a respective one of the Glue logic units.

19. The crossbar switch of claim 18, wherein each of the translation circuits is capable of receiving an opcode and a virtual address from their respective device, translating the opcode to determine whether the access request is a read or a write, and mapping the virtual address into a physical address, and forwarding the translated opcode and mapped physical address to its respective input sorting unit.

20. The crossbar switch of claim 17, wherein each of the input sorting units includes a buffer and is capable of buffering the access requests from its respective physical memory device.

21. The crossbar switch of claim 20, wherein the buffer is a first-in, first-out queue.

22. The crossbar switch of claim 20, wherein each of the input sorting units is capable of stalling its respective device when its buffer is full.

23. The crossbar switch of claim 17, wherein each merge and interleave unit further includes:

the priority generator for each input sorting unit being further capable of;

receiving the plurality of characteristics for the access request received by the input sorting unit;

receiving the plurality of operational characteristics; and

generating the composite request priority from the characteristics of the access requests and the operational characteristics;

the priority compare circuit being further capable of;

comparing the composite request priorities generated by the priority generators; and

selecting the one access request predicated on the comparison of the composite request priorities.

24. The crossbar switch of claim 17, wherein:

each back end further includes a read buffer capable of receiving and buffering read data from a respective one of the physical memory devices; and

each front end further includes an output management unit capable of receiving read data from the read buffers and forwarding the received read data to a respective one of the devices that generated the access request associated with the read data.

25. The crossbar switch of claim 17, wherein each back end further comprises a memory interface capable of receiving the selected access request from the merge and interleave unit and forwarding the selected access request to a respective one of the physical memory devices.

26. A crossbar switch, comprising a plurality of arbitration and select units, each arbitration and select unit including:

a plurality of front ends, each front end comprising;

means for processing an access request received from a respective device;

means for buffering and forwarding the processed access request;

means for receiving read data generated by the access request and forwarding the received read data to the respective device; and

a plurality of back ends, each back end comprising;

means for arbitrating among competing access requests received from the means for processing an access request, selecting one of the competing access requests, and forwarding the selected request for implementation on a respective memory device; and

means for receiving, buffering, and forwarding read data received from the respective memory device to the output management unit of the front end that issued a previously selected access request that generated the read data;

means for generating a composite request priority from a plurality of characteristics for the access requests and a plurality of operational characteristics;

means for selecting one access request; and

means for outputting the selected access request via a multiplexing means, the multiplexing means being controlled by the means for selecting the one access request;

means for storing programmable weights;

a decode unit receiving the selected request from the multiplexing means to determine whether the selected request is a register operation and, if so, to send a plurality of control and data signals to the storage means; and

means for combining register read data with request data for output.

27. The crossbar switch of claim 26, wherein each back end further comprises a memory interface through which the merge and interleave unit forwards the selected request.

28. The crossbar switch of claim 26, wherein each processing means is further capable of receiving an opcode and a virtual address from their respective device, translating the opcode to determine whether the access request is a read or a write, and mapping the virtual address into a physical address, and forwarding the translated opcode and mapped physical address to its respective input sorting unit.

29. The crossbar switch of claim 26, wherein each of the processed access request buffering means includes a buffer and is capable of buffering the access requests from its respective physical memory device.

30. The crossbar switch of claim 29, wherein the buffer is a first-in, first-out queue.

31. The crossbar switch of claim 29, wherein each of the processed access request buffering means is capable of stalling its respective device when its buffer is full.

32. The crossbar switch of claim 26, wherein each arbitration and selection unit further includes:

means for receiving the plurality of characteristics for the access request received by the input sorting unit, receiving the plurality of operational characteristics, and generating the composite request priority from the characteristics of the access requests and the operational characteristics;

means for comparing the composite request priorities generated by the priority generators, and selecting the one access request predicated on the comparison of the composite request priorities.

33. The crossbar switch of claim 26, wherein:

each back end further includes means for receiving and buffering read data from a respective one of the physical memory devices; and

each front end further includes means for receiving read data from the read buffers and forwarding the received read data to a respective one of the devices that generated the access request associated with the read data.