Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants
First Claim
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1. A computer system, comprising:
- an interconnect;
a plurality of processor nodes, coupled to the interconnect, each processor node comprising at least one processor core, each processor core having an associated memory cache for caching memory lines of information;
a plurality of input/output nodes coupled to the interconnect; and
wherein the processor nodes and the input/output nodes collectively comprise a plurality of system nodes, each of which comprises input logic that receives a first invalidation request, the invalidation request identifying a memory line of information and a patten of bits that identify a subset of the plurality of system nodes that potentially store cached copies of the identified memory line; and
processing circuitry that, responsive to receipt of the first invalidation request, determines a next node identified by the pattern of bits in the invalidation request and sends to the next node, if any, a second invalidation request corresponding to the first invalidation request, and that invalidates a cached copy of the identified memory line, if any, in the particular node of the computer system.
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Abstract
A computer system has a plurality of processor nodes and a plurality of input/output nodes. Each processor node includes a multiplicity of processor cores, an interface to a local memory system and a protocol engine implementing a predefined cache coherence protocol. Each processor core has an associated memory cache for caching memory lines of information. Each input/output node includes no processor cores, an input/output interface for interfacing to an input/output bus or input/output device, a memory cache for caching memory lines of information and an interface to a local memory subsystem. The local memory subsystem of each processor node and input/output node stores a multiplicity of memory lines of information. The protocol engine of each processor node and input/output node implements the same predefined cache coherence protocol.
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Citations
6 Claims
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1. A computer system, comprising:
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an interconnect;
a plurality of processor nodes, coupled to the interconnect, each processor node comprising at least one processor core, each processor core having an associated memory cache for caching memory lines of information;
a plurality of input/output nodes coupled to the interconnect; and
wherein the processor nodes and the input/output nodes collectively comprise a plurality of system nodes, each of which comprises input logic that receives a first invalidation request, the invalidation request identifying a memory line of information and a patten of bits that identify a subset of the plurality of system nodes that potentially store cached copies of the identified memory line; and
processing circuitry that, responsive to receipt of the first invalidation request, determines a next node identified by the pattern of bits in the invalidation request and sends to the next node, if any, a second invalidation request corresponding to the first invalidation request, and that invalidates a cached copy of the identified memory line, if any, in the particular node of the computer system. - View Dependent Claims (2, 3)
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4. A computer system, comprising:
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a plurality of multiprocessor nodes, each multiprocessor node comprising a multiplicity of processor cores, each processor core having an associated memory cache for caching memory lines of information;
a plurality of input/output nodes coupled to the plurality of multiprocessor nodes; and
wherein the multiprocessor nodes and the input/output nodes collectively comprise a plurality of system nodes, each of which comprises input logic that receives a first invalidation request, the invalidation request identifying a memory line of information and a pattern of bits for identifying a subset of the plurality of system nodes that potentially store cached copies of the identified memory line; and
processing circuitry that, responsive to receipt of the first invalidation request, determines a next node identified by the pattern of bits in the invalidation request and for sending to the next node, if any, a second invalidation request corresponding to the first invalidation request, and that invalidates a cached copy of the identified memory line, if any, in the particular node of the computer system. - View Dependent Claims (5, 6)
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Specification
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Current AssigneeSK Hynix Inc.
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Original AssigneeHewlett-Packard Development Company, L.P. (HP Inc.)
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InventorsRavishankar, Mosur K., Stets, Robert J. Jr., Nowatzyk, Andreas, Gharachorloo, Kourosh, Barroso, Luiz A.
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Primary Examiner(s)NGUYEN, THAN VINH
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Application NumberUS10/698,130Publication NumberTime in Patent Office641 DaysField of Search711141-146, 711/147, 711/117, 711/118US Class Current711/141CPC Class CodesG06F 12/0817 using directory methodsG06F 2212/621 Coherency control relating ...
