System and method for applying timing models in a static-timing analysis of a hierarchical integrated circuit design

• US 6,925,621 B2
• Filed: 06/24/2002
• Issued: 08/02/2005
• Est. Priority Date: 06/24/2002
• Status: Active Grant

• Current Assignee: Broadcom International Pte Ltd. (Broadcom, Inc.)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Batchelor, Dennis B., Mielke, David James
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Levin, Naum B.
• Application Number:
  US10/178,604
• Publication Number:
  US 20030237067A1
• Time in Patent Office: 1,135 Days
• Field of Search: 716/2, 716 4- 6, 716/18, 703/19, 703/26, 709230-232
• US Class Current: 716/103
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A system and method for automating a static-timing analysis of an integrated circuit design are provided. A representative system includes a network coupled to a plurality of data storage devices, the data storage devices containing a knowledge base that defines an integrated circuit design; a computer coupled to the network, the computer including logic for receiving information defining an integrated circuit representation from the plurality of data storage devices; and a memory element associated with the computer, the memory element configured to store logic, the logic configured to generate static-timing scripts that reflect a plurality of timing models. A representative method includes the following steps: acquiring circuit information, the circuit information comprising a plurality of functional blocks; identifying a timing model to apply to each of the plurality of functional blocks; defining the hierarchical relationships between each of the plurality of functional blocks; extracting the circuit information responsive to the identifying and defining steps to complete a simulation of each of the plurality of functional blocks; and forwarding the simulation to a static-timing engine.

Claims

1. A circuit design system, comprising:

a network coupled to a plurality of data storage devices, the data storage devices containing a knowledge base that defines an integrated circuit design;

a computer coupled to the network, the computer including logic for receiving information defining an integrated circuit representation from the plurality of data storage devices; and

a memory element associated with the computer, the memory element configured to store logic, the logic configured to generate one or more static-timing scripts that reflect a plurality of timing models responsive to one or more sentry registers inserted along conductors that traverse a boundary of a functional block within the circuit design and the expected signal timing behavior of a signal that traverses the conductor, the logic further configured to generate a static timing run script and structured timing data, wherein the static timing scripts, the static timing run script, and the structured timing data are forwarded to a static timing engine for execution.

2. The system of claim 1, wherein the knowledge base comprises a netlist, the netlist describing the relative placement of a plurality of functional blocks.

3. The system of claim 2, wherein the knowledge base comprises a hierarchical relationship between the plurality of functional blocks.

4. The system of claim 2, wherein the netlist comprises a plurality of ports.

5. The system of claim 4, wherein the netlist comprises conductors that traverse the ports.

6. The system of claim 4, wherein the netlist describes a path traversed by the conductor between the ports.

7. The system of claim 2, wherein the logic is configured to generate a run script configured to execute a static-timing engine.

8. The system of claim 7, wherein the run script includes information that controls the format of the data generated by the static-timing engine.

9. The system of claim 2, wherein the logic is responsive to a configuration file.

10. The system of claim 9, wherein the data generated by the static-timing engine is suppressed.

11. The system of claim 9, wherein the configuration file comprises a timing model identifier.

12. The system of claim 9, wherein the configuration file comprises a circuit information load identifier.

13. The system of claim 1, wherein at least one of the plurality of timing models a quantity of timing arcs that is less than the number of timing arcs identified in an abstraction of the corresponding functional block.

14. The system of claim 1, wherein at least one of the plurality of timing models comprises a subset of timing arcs internal to the functional block.

15. The system of claim 1, at least one of the plurality of timing models comprises timing arcs that traverse the functional block.

16. A method for automating static-timing analysis of an integrated circuit representation, the method comprising the steps of:

acquiring circuit information, the circuit information comprising a plurality of functional blocks and a plurality of conductors coupling the functional blocks, wherein the functional blocks are modeled by a subset of the plurality of conductors, a respective subset defined by those conductors that traverse a border of each respective functional block;

identifying a timing model to apply to each of the plurality of functional blocks responsive to at least one sentry register inserted along a conductor at the boundary of a functional block and the expected signal timing behavior of a signal that traverses the conductor;

defining the hierarchical relationships between each of the plurality of functional blocks;

extracting the circuit information responsive to the identifying and defining steps to complete a simulation of each of the plurality of functional blocks; and

forwarding one or more static-timing scripts, a static timing run script, and structured timing data to a static-timing engine.

17. The method of claim 16, wherein the circuit information comprises a relative position of the functional blocks.

18. The method of claim 16, wherein the circuit information comprises a plurality of ports, the ports defining a relative position of each of the conductors that traverse the border of a particular functional block.

19. The method of claim 16, wherein the step of identifying comprises setting a parameter in a configuration file.

20. The method of claim 16, wherein the step of defining comprises a hierarchical structure file.

21. The method of claim 20, wherein one of the plurality of functional blocks comprises a child block.

22. The method of claim 16, wherein the step of extracting is responsive to an indicator in a configuration file that identifies the location of the information associated with each functional block.

23. The method of claim 16, wherein the step of extracting is responsive to a timing model associated with each functional block.

24. The method of claim 23, wherein the timing model comprises a quantity of timing arcs that is less than the number of timing arcs identified in an abstraction of the corresponding functional block.

25. The method of claim 23, wherein the timing model comprises a timing arc internal to the functional block.

26. The method of claim 25, wherein the timing model comprises a timing arc that traverses the functional, block.

27. A computer-readable medium having a program for automatically configuring a static-timing engine to statically time an integrated circuit design, the program comprising:

logic configured to receive a representation of the integrated circuit at a functional block level;

logic configured to identify hierarchical relationships between a plurality of functional blocks of interest;

logic configured to identify each of a plurality of conductors that traverse a border of the functional blocks of interest;

logic configured to model the plurality of conductors by inserting a sentry register at a location where the conductor traverses a border of a functional block and the expected signal timing behavior of a signal that traverses the conductor;

logic configured to generate a plurality of static-timing scripts, a static timing run script, and structured timing data, the static-timing scripts configured to populate a plurality of timing models, each of the timing models configured to simulate the operation of a corresponding functional block; and

logic configured to forward the plurality of static-timing scripts, the static timing run script, and structured timing data to a static timing engine.

28. The computer-readable medium of claim 27, wherein the logic configured to generate a plurality of static-timing scripts extracts information from a knowledge base distributed across a network.

29. The computer-readable medium of claim 28, wherein the knowledge base comprises a configuration file.

30. The computer-readable medium of claim 28, wherein the knowledge base comprises a hierarchical structure file.

31. A computer aided circuit design tool, comprising:

means for acquiring a representation of an integrated circuit;

means for communicating hierarchical relationships within the representation at a functional block level;

means for identifying which of a plurality of interchangeable timing models should be applied in a static-timing analysis of the integrated circuit, wherein each of the interchangeable timing models is responsive to at least one sentry register inserted along a conductor at the boundary of a functional block and the expected signal timing behavior of a signal that traverses the conductor;

means for populating each of the interchangeable timing models; and

means for forwarding a plurality of static-timing scripts, a static timing run script, and structured timing data to a static timing engine.

32. A method for generating a run script configured to automate a static-timing analysis of an integrated circuit representation using a static timing engine, the method comprising the steps of:

configuring child block representations associated with each child block associated with a functional block of interest;

generating a top-level circuit representation responsive to at least one sentry register inserted along a conductor at the boundary of the functional block of interest and the expected signal timing behavior of a signal that traverses the conductor;

applying parasitic values to the top-level circuit representation; and

translating information stored in an integrated circuit knowledge base into a format compatible with a static timing engine, the format comprising one or more static timing scripts, a static timing run script, and structured timing data.

33. The method of claim 32, wherein the step of configuring comprises identifying a timing model to apply for each of the child block representations.

34. The method of claim 33, wherein the timing model is selected from a plurality of interchangeable models.

35. The method of claim 33, wherein the step of configuring comprises setting a first parameter in a file.

36. The method of claim 33, wherein the step of configuring is responsive to a hierarchical structure file.