Method of making a series of resonant frequency tags

• US 6,925,701 B2
• Filed: 03/13/2003
• Issued: 08/09/2005
• Est. Priority Date: 03/13/2003
• Status: Expired due to Fees

• Current Assignee: CHECKPOINT SYSTEMS, INC. (CCL Industries Incorporated)
• Original Assignee: CHECKPOINT SYSTEMS, INC. (CCL Industries Incorporated)
• Inventors: Mazoki, Gary, Matsumoto, Takeshi, Appalucci, Lawrence, Eckstein, Eric, Lendering, Peter, Bonnin, Luis Francisco Soler
• Primary Examiner(s): Kim, Paul D
• Application Number:
  US10/388,344
• Publication Number:
  US 20040177492A1
• Time in Patent Office: 880 Days
• Field of Search: 29/254.2, 295/921, 295/93, 296/021, 296/05, 296/06, 298/31, 298/32, 298/42, 298/46, 298/50, 174/260, 174/261, 324/633, 324/652, 324/655, 324/656, 336/176, 336/200, 336/229, 427/79, 427/80, 340/572.1, 340/572.5, 361/737, 361/760, 361/765, 361/766
• US Class Current: 29/602.1
• CPC Class Codes: G06K 19/0726 the arrangement including a circuit for tuning the resonance frequency of an antenna on the record carrier
• CPC Class Codes: G06K 19/07718 the record carrier being manufactured in a continuous process, e.g. using endless rolls
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G08B 13/2414 using inductive tags
• CPC Class Codes: G08B 13/2437 Tag layered structure, processes for making layered tags
• CPC Class Codes: H01F 27/40 Structural association with built-in electric component, e.g. fuse
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01F 5/003 Printed circuit coils
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/435 Solid dielectric type
• CPC Class Codes: Y10T 29/49002 Electrical device making
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49018 with other electrical component
• CPC Class Codes: Y10T 29/4902 Electromagnet, transformer or inductor
• CPC Class Codes: Y10T 29/49071 by winding or coiling
• CPC Class Codes: Y10T 29/49073 : by assembling coil and core
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path

Abstract

A method of making a resonant frequency tag which resonates at a predetermined frequency. The method involves providing a first conductive pattern having an inductive element and a first land and a second conductive pattern having a second land and a third land which are joined together by a link. The second conductive pattern is overlaid the first conductive pattern such that the second land is positioned over the first land. The third land is in electrical communication with the inductive element of the first conductive pattern. The formed resonant frequency tag is energized to determine if the tag resonates at the predetermined frequency. If the tag resonates properly, the third land is electrically coupled to the inductive element. If it does not, the second conductive pattern is adjusted so that overlapping portions of the first and second lands are changed, altering the capacitance to adjust the resonant tag frequency.

Claims

1. A method of making a series of resonant frequency tags which each resonate at substantially the same predetermined frequency, the method comprising the steps of:

(a) forming a series of first conductive patterns, the first conductive patterns all being substantially the same, each first conductive pattern comprising an inductive element and a first land, the first land having a first end connected to one end of the inductive element and a second end spaced a predetermined distance from the first end;

(b) separately forming a series of second conductive patterns, the second conductive patterns all being substantially the same and each second conductive pattern comprising a second land and a link element, the second land having a predetermined width;

(c) securing a second conductive pattern to a first conductive pattern of the series at a first predetermined location so that the second land overlies at least a portion of the first land with a dielectric therebetween to establish the plates of a capacitive element of a first tag of the series, the capacitive element having a first predetermined capacitance;

(d) measuring the resonant frequency of the tag and comparing the measured frequency with the predetermined frequency; and

(e) if the measured resonant frequency matches the predetermined frequency within a predetermined tolerance, forming the next tag of the series by securing another one of said second conductive patterns to another one of said first conductive patterns of the series by positioning the second land of said next tag over at least a portion of said first land of said next tag that corresponds to said at least one portion of said first land in said first tail, and wherein a dielectric is disposed between said first and second lands of said next tag to establish a capacitive element of said next tag, said capacitive element of said next tag having the first predetermined capacitance and then repeating steps (d) and (e) for the remainder of the series and if the measured resonant frequency does not match the predetermined frequency within the predetermined tolerance, forming the next tag of the series by securing another one of said second conductive patterns to another one of said first conductive patterns of the series by positioning the second land of said next tag over at least a portion of said first land of said next tag that does not correspond to said at least one portion of said first land in said first tag, and wherein a dielectric is disposed between said first and second lands of said next tag to establish a capacitive element of said next tag, said capacitive element of said next tag having a second predetermined capacitance and then repeating steps (d) and (e) for the remainder of the series.

2. The method as recited in claim 1, wherein each first land has a width and a length and wherein the width decreases when moving along the length from one end to the other end.

3. The method as recited in claim 2, wherein each second land is rectangular and has a length which exceeds the greatest width of the first lands.

4. The method as recited in claim 1, wherein each second conductive pattern is secured to the corresponding first conductive pattern by one of an adhesive and hot pressing.

5. The method as recited in claim 4, wherein each second conductive pattern is secured to the corresponding first conductive pattern by applying pressure, the amount of pressure being varied to control the resonant frequency of each tag.

6. The method as recited in claim 1, wherein the second conductive patterns, once formed, are initially held on a carrier sheet.

7. The method as recited in claim 1, wherein each second conductive pattern includes a dielectric layer which is placed between the second land and the first land prior to securing the second conductive pattern to the corresponding first conductive pattern.

8. The method as recited in claim 1, wherein each link element comprises a first section connected to the second land and a second section, the first and second sections of each link element being spaced apart by a gap of a predetermined minimum width and further comprising an integrated circuit including at least a first lead electrically connected to the first section of each link element and a second lead electrically connected to the second section of the link element.

9. The method as recited in claim 8, wherein an integrated circuit is secured to one of the first and second section of each link element.