Method for constructing a wafer-interposer assembly

• US 6,927,083 B2
• Filed: 02/02/2004
• Issued: 08/09/2005
• Est. Priority Date: 11/07/2000
• Status: Expired due to Fees

• Current Assignee: Transpacific Multicast, LLC
• Original Assignee: Eaglestone Partners I LLC
• Inventors: Kline, Jerry D.
• Primary Examiner(s): COLEMAN, WILLIAM D
• Application Number:
  US10/771,796
• Publication Number:
  US 20040166663A1
• Time in Patent Office: 554 Days
• Field of Search: 438/17
• US Class Current: 438/17
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/0103 Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A method for reducing the likelihood of damaging a semiconductor wafer (18) and the integrated circuit chips of the semiconductor wafer (18) during handling utilizes a wafer interposer (12) having a wafer receiving portion (28) and a handling portion (30). The wafer receiving portion (28) of the wafer interposer (12) has a plurality of contact pads (22) that are electrically and non-temporarily mechanically connected to the contact pads of the integrated circuit chips of the wafer (18). The handling portion (30) of the wafer interposer (12) extends outwardly from the wafer receiving portion (28) such that the handling portion (30) is accessible to handling equipment without the handling equipment contacting the attached wafer (18).

Claims

1. A method for constructing a wafer-interposer assembly comprising the steps of:

providing a wafer having a plurality of integrated circuit chips each having a plurality of contact pads; and

connecting the wafer to a wafer receiving portion of a wafer interposer to form a wafer-interposer assembly by electrical and non-temporary mechanical connection of at least some of the contact pads of the integrated circuit chips with contact pads of the wafer receiving portion, the wafer interposer having a handling portion extending outwardly from the wafer receiving portion.

2. The method as recited in claim 1 further comprising the step of magnetically accessing the wafer-interposer assembly via at least one magnet operably associated with the handling portion of the wafer interposer.

3. The method as recited in claim 1 further comprising the step of securably coupling to the wafer-interposer assembly via at least one locking member operably associated with the handling portion of the wafer interposer.

4. The method as recited in claim 1 further comprising the step of disposing at least one stiffening member within the handling portion of the wafer interposer.

5. The method as recited in claim 1 further comprising the step of moving the wafer-interposer assembly using a set of bearings in the handling portion of the wafer interposer.

6. The method as recited in claim 1 further comprising the step of disposing a cushioning member around at least part of the handling portion of the wafer interposer.

7. The method as recited in claim 1 further comprising the step of removably attaching a cover to the handling portion of the wafer interposer that extends across the wafer receiving portion.

8. The method as recited in claim 1 further comprising the step of testing the integrated circuit chips of the wafer without contacting the integrated circuit chips.

9. A method for reducing the likelihood of damaging a wafer during handling comprising the steps of:

providing a wafer having a plurality of integrated circuit chips each having a plurality of contact pads;

connecting the wafer to a wafer receiving portion of a wafer interposer to form a wafer-interposer assembly by electrical and non-temporary mechanical connection of at least some of the contact pads of the integrated circuit chips with contact pads of the wafer receiving portion; and

accessing a handling portion of the wafer interposer that is operably associated with the wafer receiving portion without contacting the wafer.

10. The method as recited in claim 9 wherein the step of accessing the handling portion of the wafer interposer without contacting the wafer further comprises accessing at least one slot operably associated with the handling portion of the wafer interposer.

11. The method as recited in claim 9 wherein the step of accessing the handling portion of the wafer interposer without contacting the wafer further comprises accessing at least one hole operably associated with the handling portion of the wafer interposer.

12. The method as recited in claim 9 wherein the step of accessing the handling portion of the wafer interposer without contacting the wafer further comprises accessing at least one receiving member operably associated with the handling portion of the wafer interposer.

13. The method as recited in claim 9 wherein the step of accessing the handling portion of the wafer interposer without contacting the wafer further comprises accessing at least one magnet operably associated with the handling portion of the wafer interposer.

14. The method as recited in claim 9 wherein the step of accessing the handling portion of the wafer interposer without contacting the wafer further comprises securably coupling to the wafer-interposer assembly via at least one locking member operably associated with the handling portion of the wafer interposer.

15. The method as recited in claim 9 further comprising the step of disposing at least one stiffening member within the handling portion of the wafer interposer.

16. The method as recited in claim 9 further comprising the step of moving the wafer-interposer assembly using a set of bearings in the handling portion of the wafer interposer.

17. The method as recited in claim 9 further comprising the step of disposing a cushioning member around at least part of the handling portion of the wafer interposer.

18. The method as recited in claim 9 further comprising the step of removably attaching a cover to the handling portion of the wafer interposer that extends across the wafer receiving portion.

19. The method as recited in claim 9 further comprising the step of testing the integrated circuit chips of the water without contacting the integrated circuit chips.

20. A method for constructing chip assemblies comprising the steps of:

providing a wafer having a plurality of integrated circuit chips each having a plurality of contact pads;

connecting the wafer to a wafer receiving portion of a wafer interposer to form a wafer-interposer assembly by electrical and non-temporary mechanical connection of at least some of the contact pads of the integrated circuit chips with contact pads of the wafer receiving portion;

accessing a handling portion of the wafer interposer that extends outwardly from the wafer receiving portion without contacting the wafer;

separating the handling portion of the wafer interposer from the wafer interposer; and

singulating the wafer-interposer assembly into a plurality of chip assemblies, each chip assembly including at least one of the integrated circuit chips and a portion of the water interposer.

21. The method as recited in claim 20 wherein the step of separating the handling portion occurs prior to the step of singulating the wafer-interposer assembly.

22. The method as recited in claim 20 wherein the step of separating the handling portion occurs substantially simultaneously with the step of singulating the wafer-interposer assembly.

23. The method as recited in claim 20 further comprising the step of mounting at least one of the chip assemblies on a substrate.

24. The method as recited in claim 20 wherein the step of accessing the handling portion of the water interposer without contacting the wafer further comprises accessing at least one slot operably associated with the handling portion of the wafer interposer.

25. The method as recited in claim 20 wherein the step of accessing the handling portion of the wafer interposer without contacting the wafer further comprises accessing at least one hole operably associated with the handling portion of the wafer interposer.

26. The method as recited in claim 20 wherein the step of accessing the handling portion of the wafer interposer without contacting the wafer further comprises accessing at least one receiving member operably associated with the handling portion of the wafer interposer.