Method for forming a contact line and buried contact line in a CMOS imager

• US 6,927,090 B2
• Filed: 08/11/2003
• Issued: 08/09/2005
• Est. Priority Date: 12/08/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Pham, Long
• Application Number:
  US10/637,529
• Publication Number:
  US 20040046104A1
• Time in Patent Office: 729 Days
• Field of Search: 438/57, 438/59
• US Class Current: 438/59
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output transistor. The doped polysilicon contact line in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a doped polysilicon contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

Claims

1. A method of forming a contact line in a CMOS imager, comprising the steps of:

providing a substrate having a first conductivity;

forming a diffusion region having a second conductivity in said substrate;

forming an insulating layer over said substrate;

forming a gate of an output transistor over said substrate;

selectively removing at least a portion of said insulating layer over said diffusion region;

selectively removing at least a portion of said insulating layer over the gate of said output transistor; and

forming a conductive layer of doped polysilicon over at least a portion of said insulating layer to connect said diffusion region and the gate of said output transistor, wherein a contact region is formed between said conductive layer of doped polysilicon and said diffusion region by the diffusion of dopants from said conductive layer of doped polysiicon into said diffusion region.

2. The method according to claim 1, wherein said insulating layer is silicon dioxide.

3. The method according to claim 1, further comprising forming a composite layered doped polysilicon/barrier metal silicide/metal structure to connect said diffusion region with the gate of said output transistor.

4. The method according to claim 1, wherein said substrate of a first conductivity includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

5. The method according to claim 1, further comprising forming a refractory metal silicide layer around the periphery of said conductive layer of doped polysilicon.

6. The method according to claim 5, further comprising forming an insulating layer around the periphery of said refractory metal silicide layer.

7. The method according to claim 1, wherein said first conductivity type is p-type and said second conductivity type is n-type.

8. The method according to claim 1, wherein said output transistor is a source follower transistor formed adjacent to said diffusion region.

9. The method according to claim 1, wherein said insulating layer is removed by etching.

10. A method of forming a buried contact line in a CMOS imager, comprising the steps of:

providing a substrate having a first conductivity;

forming a diffusion region having a second conductivity in said substrate;

forming an insulating layer over said substrate;

forming a gate of an output transistor over said substrate;

selectively removing at least a portion of said insulating layer to form a first trench over said diffusion region;

selectively removing at least a portion of said insulating layer to form a second trench over the gate of said output transistor;

forming first and second conductive doped polysilicon plugs in said first and second trenches, respectively; and

forming a metal interconnector over said insulating layer to connect said diffusion region and the gate of said output transistor, wherein a contact region is formed between said first doped polysilicon plug and said diffusion region by the diffusion of dopants from said first doped polysilicon plug into said diffusion region.

11. The method according to claim 10, wherein said insulating layer is silicon dioxide.

12. The method according to claim 10, wherein said substrate of a first conductivity includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

13. The method according to claim 10, wherein said first conductivity type is p-type and said second conductivity type is n-type.

14. The method according to claim 10, wherein said output transistor is a source follower transistor formed adjacent to said diffusion region.

15. The method according to claim 10, wherein said insulating layer is removed by etching.

16. The method according to claim 10, wherein said metal interconnector comprises a tungsten metal.

17. The method according to claim 10, wherein said metal interconnector comprises at least one of Ti, Al, W, Cu, nitrides thereof, mixtures thereof and alloys thereof.

18. The method according to claim 16, wherein said metal interconnector is formed by sputtering.

19. The method according to claim 18, wherein said metal interconnector is formed by sputtering.

20. A method of forming a contact line in a CMOS imager, comprising the steps of:

providing a semiconductor substrate doped to a first conductivity;

forming a floating diffusion region of a second conductivity in said substrate;

forming an insulating layer over at least a portion of said substrate;

forming a gate of a source follower transistor adjacent to said floating diffusion region;

selectively removing at least a portion of said insulating layer over the gate of said source follower transistor;

selectively removing at least a portion of said insulating layer over said floating diffusion region; and

forming a doped polysilicon layer over at least a portion of said insulating layer to connect said floating diffusion region and the gate of said source follower transistor, wherein a contact region is formed between said doped polysilicon layer and said floating diffusion region by the diffusion of dopants from said doped polysilicon layer into said floating diffusion region.

21. A The method according to claim 20, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

22. A method of forming a buried contact line in a CMOS imager, comprising the steps of:

providing a substrate having a first conductivity;

forming a diffusion region having a second conductivity in said substrate;

forming an insulating layer over at least a portion of said substrate, wherein said insulating layer is formed over at least a portion of said diffusion region;

forming an output transistor over said substrate;

selectively removing at least a portion of said insulating layer to form a diffusion contact area over said diffusion region; and

forming a conductive layer of doped polysilicon directly in said removed portion of said insulating layer to connect said diffusion region and said output transistor, wherein dopants from said conductive layer of doped polysilicon diffuse into said diffusion contact area over said diffusion region.

23. The method according to claim 22, wherein said insulating layer is silicon dioxide.

24. The method according to claim 22, further comprising forming a refractory metal silicide layer over a periphery of said conductive layer of doped polysilicon.

25. A The method according to claim 22, wherein said first conductivity type is p-type and said second conductivity type is n-type.

26. The method according to claim 22, wherein said output transistor is a source follower transistor formed adjacent to said diffusion region.

27. The method according to claim 22, wherein said insulating layer is removed by etching.