Solution-processed thin film transistor formation method

• US 6,927,108 B2
• Filed: 07/09/2003
• Issued: 08/09/2005
• Est. Priority Date: 07/09/2003
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Weng, Jian-gang, Prasad, Ravi, Addington, Cary G, Cheung, Man Ho
• Primary Examiner(s): Fourson, George
• Assistant Examiner(s): Kebede, Brook
• Application Number:
  US10/617,114
• Publication Number:
  US 20050009248A1
• Time in Patent Office: 762 Days
• Field of Search: 438149-164, 438/758, 438/761, 438/763, 438/767, 438/779, 438/782, 438/789, 438/790, 438/690, 257/E21.041, 257/E29.117, 257/E29.202, 257/E29.273, 257/E51.005, 257/E29.151, 216/65, 216/66, 216/94, 427/96, 427/402
• US Class Current: 438/164
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 71/231 by etching of existing layers
• CPC Class Codes: H10K 71/60 Forming conductive regions or layers, e.g. electrodes
• CPC Class Codes: H10K 77/111 Flexible substrates
• CPC Class Codes: H10K 85/113 Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
• CPC Class Codes: H10K 85/1135 Polyethylene dioxythiophene [PEDOT]; Derivatives thereof

Abstract

An exemplary solution-processed thin film transistor formation method of the invention forms conductive solution-processed thin film material contacts, semiconductor solution-processed thin film material active regions, and dielectric solution-processed thin film material isolations in a sequence and organization to form a solution-processed thin film structure capable of transistor operation. During or after the formation of the transistor structure, laser ablation is applied to one or more of the conductive solution-processed thin film material contacts, the semiconductor solution-processed thin film material active regions and the dielectric solution-processed thin film material isolations to pattern or complete patterning of a material being selectively ablated.

Claims

1. A solution-processed thin film transistor formation method, comprising steps of:

forming conductive solution-processed thin film contacts, semiconductor solution-processed thin film active regions, and dielectric solution-processed thin film isolations in a sequence and organization to form a solution-processed thin film structure capable of transistor operation; and

selectively ablating one or more of the semiconductor solution-processed thin film active regions and the dielectric solution-processed thin film isolations to pattern or complete patterning of a material being selectively ablated, wherein said step of selectively ablating is carried out during or after said step of forming.

2. The method of claim 1, wherein said step of selectively ablating is applied to complete patterning of a material roughly patterned when deposited.

3. The method of claim 2, wherein the material roughly patterned when deposited is patterned as a result of an inkjet deposition process.

4. The method of claim 2, wherein the material roughly patterned when deposited is patterned as a result of a spin coat deposition process.

5. The method of claim 1, repeated to form a plurality of thin film structures capable of transistor operation and further comprising a step of forming device isolations by ablating material between structures.

6. The method of claim 5, further comprising a step of filling the device isolations with dielectric solution-processed thin film material.

7. The method of claim 5, wherein the conductive solution-processed thin film contacts are patterned to form a circuit interconnect pattern.

8. The method of claim 1, wherein said steps of forming and ablating comprise the following steps:

depositing drain and source conductive solution-processed thin film material upon a substrate;

selectively ablating a transistor channel in the drain and source conductive solution-processed thin films to form drain and source contacts;

depositing active region semiconductor solution-processed thin film material over the drain and source contacts and the substrate;

depositing isolation region dielectric solution-processed thin film material over the semiconductor solution-processed thin film material; and

depositing gate conductive solution-processed thin film material upon the isolation region dielectric to form a gate contact.

9. The method of claim 8, wherein said steps of depositing drain and source conductive solution-processed thin film material and depositing gate conductive material solution-processed thin film material comprise inkjet printing conductive solution-processed thin film material.

10. The method of claim 9, wherein:

said step of depositing active region semiconductor solution-processed thin film material comprises spin coating dielectric solution-processed thin film material; and

said step of depositing isolation region dielectric solution-processed thin film material comprises spin coating dielectric solution-processed thin film material.

11. The method of claim 8, wherein the transistor channel is formed to be 5 μ

m or less wide.

12. The method of claim 1, wherein said steps of forming and ablating comprise the following steps:

depositing gate conductive solution-processed thin film material upon a substrate;

depositing isolation region dielectric solution-processed thin film material over the gate conductive solution-processed thin film material and the substrate;

depositing active region semiconductor solution-processed thin film material over the isolation region dielectric; and

depositing drain and source conductive solution-processed thin film material upon the active region semiconductor solution-processed thin film material; and

selectively ablating a transistor channel in the drain and source conductive solution-processed thin film material to form drain and source contacts.

13. The method of claim 12, wherein said steps of depositing drain and source conductive solution-processed thin films and depositing gate conductive solution-processed thin film materials comprise inkjet printing conductive solution-processed thin film material.

14. The method of claim 13, wherein:

said step of depositing active region semiconductor solution-processed thin film material comprises spin coating semiconductor solution-processed thin film material and

said step of depositing isolation region dielectric solution-processed thin film material comprises spin coating dielectric solution-processed thin film material.

15. The method of claim 1, wherein said steps of forming and ablating comprise the following steps:

depositing gate conductive solution-processed thin film material upon a substrate;

depositing isolation region dielectric solution-processed thin film material over the gate conductive solution-processed thin film material and the substrate;

depositing drain and source conductive solution-processed thin film material upon the isolation region dielectric solution-processed thin film material;

selectively ablating a transistor channel in the drain and source conductive solution-processed thin film material to form drain and source contacts;

depositing active region semiconductor solution-processed thin film material over the drain and source conductive solution-processed thin film material and the isolation dielectric.

16. The method of claim 15, wherein said steps of depositing source and source drain conductive solution-processed thin films and depositing gate conductive solution-processed thin film material comprise inkjet printing conductive solution-processed thin film material.

17. The method of claim 16, wherein;

said step of depositing active region semiconductor solution-processed thin film material comprises spin coating semiconductor solution-processed thin film material; and

said step of depositing isolation region dielectric solution-processed thin film material comprising spin coating dielectric solution-processed thin film material.

18. The method of claim 1, wherein said step of selectively ablating uses a laser wavelength tuned to be absorbed by material being ablated and to minimally damage material underlying material being ablated.

19. The method of claim 1, wherein said step of selectively ablating is conducted through an optical mask to ablate multiple features simultaneously.

20. The method of claim 1, wherein said step of selectively ablating is carried out while varying one or both of a laser wavelength and intensity.

29. The method of claim 1, wherein selectively ablating includes a conductive solution-processed thin film contact.

21. A solution-processed thin film transistor formation method, comprising steps of:

forming solution-processed thin film layers into a transistor structure wherein the transistor structure includes a semiconductor solution-processed thin film active region, and a dielectric solution-processed thin film isolation; and

during said forming, patterning the semiconductor solution-processed thin film active region and the dielectric solution-processed thin film isolation via laser ablation, using laser wavelength tuned to be absorbed by material being patterned and to minimally damage material underlying material being patterned.

22. The method of claim 21, wherein said step of patterning is applied to complete patterning of a material roughly patterned when deposited.

23. The method of claim 22, wherein the material roughly patterned when deposited is patterned as a result of an inkjet deposition process.

24. The method of claim 22, wherein the material roughly patterned when deposited is patterned as a result of a spin coat deposition process.

25. The method of claim 21, repeated to form a plurality of thin film structures capable of transistor operation and further comprising a step of forming device isolations by ablating material between structures.

26. The method of claim 25, further comprising a step of filling said device isolations with dielectric solution-processed thin film material.

27. The method of claim 21, wherein said step of patterning is conducted through an optical mask to ablate multiple features simultaneously.

28. The method of claim 21, wherein said step of patterning is carried out while varying one or both of a laser wavelength and intensity.

30. The method of claim 21, wherein the transistor structure includes a solution-processed thin film contact.